VARYING ENERGY BARRIERS OF MAGNETIC TUNNEL JUNCTIONS (MTJs) IN DIFFERENT MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) ARRAYS IN A SEMICONDUCTOR DIE TO FACILITATE USE OF MRAM FOR DIFFERENT MEMORY APPLICATIONS

ABSTRACT

Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.

BACKGROUND I. Field of the Disclosure

The technology of the disclosure relates generally to magneto-resistiverandom access memory (MRAM), and more particularly to magnetic tunneljunctions (MTJs) employed in MRAM.

II. Background

Semiconductor storage devices are used in integrated circuits (ICs) inelectronic devices to provide data storage. One example of asemiconductor storage device is magneto-resistive random access memory(MRAM). MRAM is non-volatile memory in which data is stored byprogramming a magnetic tunnel junction (MTJ) as part of an MRAM bitcell. One advantage of MRAM is that MTJs in MRAM bit cells can retainstored information even when power is turned off. This is because datais stored in the MTJ as a small magnetic element rather than as anelectric charge or current.

In this regard, an MTJ comprises a free ferromagnetic layer (“freelayer”) disposed above or below a fixed or pinned ferromagnetic layer(“pinned layer”). The free and pinned layers are separated by a tunneljunction or barrier formed by a thin non-magnetic dielectric layer. Themagnetic orientation of the free layer can be changed, but the magneticorientation of the pinned layer remains fixed or “pinned.” Data can bestored in the MTJ according to the magnetic orientation between the freeand pinned layers. When the magnetic orientations of the free and pinnedlayers are anti-parallel (AP) to each other, a first memory state exists(e.g., a logical ‘1’). When the magnetic orientations of the free andpinned layers are parallel (P) to each other, a second memory stateexists (e.g., a logical ‘0’). The magnetic orientations of the free andpinned layers can be sensed to read data stored in the MTJ by sensing aresistance when current flows through the MTJ. Data can also be writtenand stored in the MTJ by applying a magnetic field to change theorientation of the free layer to either a P or AP magnetic orientationwith respect to the pinned layer.

Recent developments in MTJ devices involve spin transfer torque(STT)-MRAM devices. In STT-MRAM devices, the spin polarization ofcarrier electrons, rather than a pulse of a magnetic field, is used toprogram the state stored in the MTJ (i.e., a ‘0’ or a ‘1’). FIG. 1illustrates an STT-MTJ device 100 (referred to as “MTJ 100”). The MTJ100 is provided as part of an MRAM bit cell 102 to store non-volatiledata. An access transistor 104 (e.g., an n-type metal-oxidesemiconductor (MOS) (NMOS) transistor) is provided to control readingand writing to the MTJ 100. A drain D of the NMOS access transistor 104is coupled to a bottom electrode 106 of the MTJ 100, which is coupled toa pinned layer 108, for example. A word line WL is coupled to a gate Gof the access transistor 104. A source S of the access transistor 104 iscoupled to a voltage source V_(S) through a source line SL. The voltagesource V_(S) provides a voltage V_(SL) on the source line SL. A bit lineBL is coupled to a top electrode 110 of the MTJ 100, which is coupled toa free layer 112, for example. The pinned layer 108 and the free layer112 are separated by a tunnel barrier 114. The pinned layer 108, thetunnel barrier 114, and the free layer 112 of the MTJ 100 form an MTJstack 116.

With continuing reference to FIG. 1, when writing data to the MTJ 100,the gate G of the access transistor 104 is activated by activating theword line WL. A voltage differential between a voltage V_(BL) on the bitline BL and the voltage V_(SL) on the source line SL is applied. As aresult, a write current I_(w) is generated between the drain D and thesource S of the access transistor 104. If the magnetic orientation ofthe MTJ 100 in FIG. 1 is to be changed from AP to P, a write current(I_(AP-P)) flowing from the free layer 112 to the pinned layer 108 isgenerated, which induces an STT at the free layer 112 to change themagnetic orientation of the free layer 112 to P with respect to thepinned layer 108. If the magnetic orientation is to be changed from P toAP, a current I_(P-AP) flowing from the pinned layer 108 to the freelayer 112 is produced, which induces an STT at the free layer 112 tochange the magnetic orientation of the free layer 112 to AP with respectto the pinned layer 108.

The write current I_(w) can change the magnetic orientation of the freelayer 112 by transferring a sufficient amount of energy from the writecurrent I_(w) to the free layer 112 of the MTJ 100. This amount ofenergy is called an energy barrier E_(b) of the MTJ 100. The energybarrier E_(b) of the MTJ 100 is the amount of energy required to switchthe magnetic orientation of the MTJ 100. The energy barrier E_(b) isbased in part on intrinsic characteristics of the MTJ stack 116. Forexample, varying material types, heights, and/or widths of the MTJ stack116 can vary the energy barrier E_(b) of the MTJ 100. The energy barrierE_(b) of the MTJ 100 can also be varied by external influences, such asambient temperature, for example.

Aspects of device performance, such as data retention rates and accesstimes, can be controlled by varying the energy barriers of MTJs, such asthe energy barrier E_(b) of the MTJ 100 in FIG. 1. Providing an MTJhaving a higher energy barrier allows the MTJ to have a higher dataretention rate, because a higher energy barrier increases the amount ofenergy required to change the magnetic orientation of the MTJ, makingthe MTJ more resilient to external effects such as temperaturevariation, leakage current, and stray capacitance. However, providing anMTJ having a higher energy barrier can also result in slower accesstimes, because the write current must be generated through the MTJ for alonger period of time to transfer an amount of energy sufficient tochange the magnetic orientation of the MTJ. Thus, for example, if theMTJ 100 of the MRAM bit cell 102 in FIG. 1 is fabricated such that ithas a higher energy barrier E_(b), the MRAM bit cell 102 will haveslower access times and a higher data retention rate compared to an MRAMbit cell that employs an MTJ having a lower energy barrier. Conversely,if the MTJ 100 of the MRAM bit cell 102 is fabricated such that it has alower energy barrier E_(b), the MRAM bit cell 102 will have fasteraccess times and a lower data retention rate compared to an MRAM bitcell that employs an MTJ having a higher energy barrier.

In this manner, MTJs having a higher energy barrier may be better suitedfor memory applications requiring higher data retention rates and sloweraccess times than for memory applications requiring faster access timesand lower data retention rates. For example, an MTJ having a higherenergy barrier may be better suited for a memory application such aseFlash memory, which requires a higher data retention rate at a tradeoffcost of slower access times, than for a memory application such as mainmemory, which requires faster access times at a tradeoff cost of lowerdata retention rates. In contrast, an MTJ having a lower energy barriermay be better suited for a memory application requiring faster accesstimes at a tradeoff cost of a lower data retention rate. For example,level 2 (L2) and level 3 (L3) cache memory in a processor-based systemmay be specified to operate with faster access times, whereas mainmemory may be specified to have increased data retention as anacceptable tradeoff to faster access times. Thus, MRAM having a lowerenergy barrier might be better suited for L2/L3 cache memory than formain memory. However, since advanced IC designs place multiple types ofmemory proximate on the same IC, such as system-on-a-chip (SoC)technologies, the lower resolution limits of conventional fabricationprocesses can force different MRAM arrays to be fabricated with the sameMTJ stack, resulting in different MRAM arrays having the same heights,widths, and other characteristics in proximity to one another.Consequently, the energy barriers of the MTJ stacks used in differenttypes of memory are required to be the same and have essentially thesame performance, although not optimal nor desired.

SUMMARY OF THE DISCLOSURE

Aspects disclosed in the detailed description include varying energybarriers of magnetic tunnel junctions (MTJs) in differentmagneto-resistive random access memory (MRAM) arrays in a semiconductordie to facilitate use of MRAM for different memory applications.Different memory applications may require different tradeoffs betweenaccess times and data retention performance as an example, where usingMTJ stacks having the same energy barrier in these different memoryapplications may not allow the desired differences in performance to berealized. Thus, in this regard, in exemplary aspects disclosed herein,to facilitate use of MRAM for different types of memories havingdifferent performance requirements in a semiconductor die, the energybarriers of MTJs that form the MRAM bit cells in different MRAM arraysin the semiconductor die are varied. The energy barrier of an MTJ in anMRAM bit cell affects the write performance of the MRAM bit cell,because the amount of switching current required to switch the magneticorientation of a free layer of the MTJ is a function of its energybarrier. Thus, by varying energy barriers of MTJs in MRAM bit cells indifferent MRAM arrays in a semiconductor die, different MRAM arrays maybe used for different types of memory provided in the semiconductor diewhile still achieving distinct performance specifications, such asaccess times, data retention rates, bit cell endurances, arraydensities, and/or power consumption rates, as examples. The energybarrier of an MTJ in an MRAM bit cell can be varied by varying thematerials, heights, widths, and/or other characteristics of MTJ stacks.

In other aspects disclosed herein, MTJs having different energy barriersare fabricated in the same layer(s) of the semiconductor die to avoidhaving to provide additional layers in the semiconductor die fordifferent MRAMs. In one example, to fabricate MTJs having differentenergy barriers in the same layer(s) of the semiconductor die, afabrication process is employed that includes forming a first blockinglayer over a second bottom via, which is in an interconnect layer of asemiconductor die. Once the second bottom via is covered by the firstblocking layer, a first MTJ stack film is deposited over a first bottomvia in the interconnect layer of the semiconductor die. A portion of thefirst MTJ stack film is then removed to form a first MTJ stack from thefirst MTJ stack film. The first MTJ stack is then masked by a hard mask,and a second MTJ stack film is deposited over the second bottom via. Aportion of the second MTJ stack film is then removed to form a secondMTJ stack from the second MTJ stack film. Each MTJ stack can be formedat varying heights and/or widths, and from varying combinations ofmaterials, as examples, such that the first MTJ stack can have an energybarrier different from the second MTJ stack. In this manner, the MTJshaving different energy barriers can provide memory devices havingvarying performance specifications in the same layer(s) of asemiconductor die.

In this regard in one exemplary aspect, a semiconductor die comprising afirst MTJ stack and a second MTJ stack is provided. The first MTJ stackcomprises a first pinned layer having a first pinned layer magneticmoment, a first free layer having a first free layer magnetic moment,and a first tunnel barrier layer disposed between the first pinned layerand the first free layer. The first MTJ stack has a first energybarrier. The second MTJ stack comprises a second pinned layer having asecond pinned layer magnetic moment, a second free layer having a secondfree layer magnetic moment, and a second tunnel barrier layer disposedbetween the second pinned layer and the second free layer. The secondMTJ stack has a second energy barrier different from the first energybarrier.

In another exemplary aspect, a semiconductor die comprising a firstmeans for storing data and a second means for storing data is provided.The first means for storing data comprises a first means for storing afixed magnetic moment having a first fixed magnetic moment, a firstmeans for storing a programmable magnetic moment having a firstprogrammable magnetic moment, and a first means for transferring spinpolarization of electrons disposed between the first means for storing afixed magnetic moment and the first means for storing a programmablemagnetic moment. The first means for storing data has a first energybarrier. The second means for storing data comprises a second means forstoring a fixed magnetic moment having a second fixed magnetic moment, asecond means for storing a programmable magnetic moment having a secondprogrammable magnetic moment, and a second means for transferring spinpolarization of electrons disposed between the second means for storinga fixed magnetic moment and the second means for storing a programmablemagnetic moment. The second means for storing data has a second energybarrier different from the first energy barrier.

In another exemplary aspect, a method of varying energy barriers of MTJsin different MRAM array in a semiconductor die is provided. The methodcomprises forming a first blocking layer over a second via of a secondMRAM array, wherein the second via is in an interconnect layer of thesemiconductor die. A first MTJ stack film is deposited over a first viaof a first MRAM array and at least a portion of the first blockinglayer. The first via is in the interconnect layer of the semiconductordie. A first top electrode film is deposited over the first MTJ stackfilm. A first mask is deposited over a portion of the first topelectrode film over the first MTJ stack film over the first via. Aportion of the first top electrode film and a portion of the first MTJstack film not under the first mask are removed to form a first topelectrode layer over a first MTJ stack over the first via of the firstMRAM array. At least a portion of the first blocking layer over thesecond via of the second MRAM array is removed. A second MTJ stack filmis deposited over the second via of the second MRAM array. A second topelectrode film is deposited over the second MTJ stack film. A secondmask is then deposited over a portion of the second top electrode filmover the second MTJ stack film over the second via. A portion of thesecond top electrode film and a portion of the second MTJ stack film notunder the second mask are removed to form a second top electrode layerover a second MTJ stack over the second via of the second MRAM array.

In another exemplary aspect, a central processing unit (CPU) systemcomprising a system bus, at least one CPU core communicatively coupledto the system bus, a memory controller communicatively coupled to thesystem bus, and a memory system communicatively coupled to the systembus is provided. The memory system comprises a first MRAM bit cell of afirst MRAM array and a second MRAM bit cell of a second MRAM array. Thefirst MRAM bit cell of the first MRAM array comprises a first MTJ stack,a first MTJ, and a first access transistor. The first MTJ stackcomprises a first pinned layer having a first pinned layer magneticmoment, a first free layer having a first free layer magnetic moment,and a first tunnel barrier layer disposed between the first pinned layerand the first free layer. The first MTJ stack has a first energybarrier. The first MTJ comprises a first top electrode layer and a firstbottom electrode layer, wherein the first MTJ stack is disposed betweenthe first top electrode layer and the first bottom electrode layer. Thefirst access transistor comprises a first gate, a first source, and afirst drain. The first access transistor is coupled to the first MTJ.The second MRAM bit cell of the second MRAM array comprises a second MTJstack, a second MTJ, and a second access transistor. The second MTJstack comprises a second pinned layer having a second pinned layermagnetic moment, a second free layer having a second free layer magneticmoment, and a second tunnel barrier layer disposed between the secondpinned layer and the second free layer. The second MTJ stack has asecond energy barrier different from the first energy barrier. Thesecond MTJ comprises a second top electrode layer and a second bottomelectrode layer, wherein the second MTJ stack is disposed between thesecond top electrode layer and the second bottom electrode layer. Thesecond access transistor comprises a second gate, a second source, and asecond drain.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic diagram of an exemplary magneto-resistive randomaccess memory (MRAM) bit cell that can be provided in an MRAM array;

FIG. 2A is top-view diagram of an exemplary semiconductor die includingmultiple MRAM arrays, each including a plurality of MRAM bit cellshaving varying energy barriers among the MRAM arrays to facilitate useof MRAM for different memory applications;

FIG. 2B is a cross-sectional, side-view diagram of the semiconductor diein FIG. 2A illustrating exemplary magnetic tunnel junction (MTJ) stacksin the plurality of MRAM bit cells of the MRAM arrays;

FIG. 3 is a flowchart illustrating an exemplary process of fabricatingthe MTJ stacks in the semiconductor die in FIG. 2B;

FIGS. 4A-4G are cross-sectional diagrams illustrating exemplary processsteps of fabricating a first MTJ stack of a first MRAM array in a metallayer of a semiconductor die as shown in FIG. 2B according to theexemplary fabrication process in FIG. 3;

FIGS. 4H-4L are cross-sectional diagrams illustrating exemplary processsteps of fabricating a second MTJ stack of a second MRAM array in themetal layer of the semiconductor die as shown in FIG. 2B according tothe exemplary fabrication process in FIG. 3;

FIGS. 4M-4Q are cross-sectional diagrams illustrating exemplary processsteps of fabricating a third MTJ stack of a third MRAM array in themetal layer of the semiconductor die as shown in FIG. 2B;

FIGS. 4R-4S are cross-sectional diagrams illustrating exemplary processsteps of fabricating each MTJ stack in the semiconductor die shown inFIG. 2B such that each MTJ stack has varying widths and material typesto provide an energy barrier of each MTJ stack different from an energybarrier of another MTJ stack;

FIGS. 5A-5R are cross-sectional diagrams illustrating alternativeexemplary process steps of fabricating the multiple MTJ stacks for usein MRAM bit cells in a plurality of MRAM bit cells in different MRAMarrays in a semiconductor die having varying energy barriers as shown inFIG. 2B;

FIGS. 6A-6C are cross-sectional diagrams illustrating exemplary processsteps of fabricating MRAM bit cells having a spacer film disposed overan interconnect layer and over MTJ stacks in different MRAM arrayshaving varying energy barriers as provided in FIGS. 2A and 2B;

FIGS. 7A-7D are cross-sectional diagrams illustrating exemplary processsteps of fabricating MRAM bit cells having a spacer film over aninterconnect layer and a top via over MTJ stacks in different MRAMarrays having varying energy barriers as provided in FIGS. 2A and 2B;

FIGS. 8A-8C are cross-sectional diagrams illustrating exemplary processsteps of fabricating MRAM bit cells from MTJ stacks having varyingenergy barriers in different MRAM arrays as provided in FIGS. 2A and 2B,wherein a top surface of an interconnect layer is exposed from a spacerfilm;

FIGS. 9A-9D are cross-sectional diagrams illustrating exemplary processsteps of fabricating MRAM bit cells having a top surface of aninterconnect layer exposed from a spacer film and a top via over MTJstacks in different MRAM arrays having varying energy barriers asprovided in FIGS. 2A and 2B; and

FIG. 10 is a block diagram of an exemplary processor-based system thatcan include MTJ stacks having varying energy barriers that can beprovided in MTJs in MRAM bit cells in different MRAM arrays to providedifferent types of memory in a semiconductor die while still achievingdistinct performance specifications.

DETAILED DESCRIPTION

With reference now to the drawing figures, several exemplary aspects ofthe present disclosure are described. The word “exemplary” is usedherein to mean “serving as an example, instance, or illustration.” Anyaspect described herein as “exemplary” is not necessarily to beconstrued as preferred or advantageous over other aspects.

Aspects disclosed in the detailed description include varying energybarriers of magnetic tunnel junctions (MTJs) in differentmagneto-resistive random access memory (MRAM) arrays in a semiconductordie to facilitate use of MRAM for different memory applications.Different memory applications may require different tradeoffs betweenaccess times and data retention performance as an example, where usingMTJ stacks having the same energy barrier in these different memoryapplications may not allow the desired differences in performance to berealized. Thus, in this regard, in exemplary aspects disclosed herein,to facilitate use of MRAM for different types of memories havingdifferent performance requirements in a semiconductor die, the energybarriers of MTJs that form the MRAM bit cells in different MRAM arraysin the semiconductor die are varied. The energy barrier of an MTJ in anMRAM bit cell affects the write performance of the MRAM bit cell,because the amount of switching current required to switch the magneticorientation of a free layer of the MTJ is a function of its energybarrier. Thus, by varying energy barriers of MTJs in MRAM bit cells indifferent MRAM arrays in a semiconductor die, different MRAM arrays maybe used for different types of memory provided in the semiconductor diewhile still achieving distinct performance specifications, such asaccess times, data retention rates, bit cell endurances, arraydensities, and/or power consumption rates, as examples. The energybarrier of an MTJ in an MRAM bit cell can be varied by varying thematerials, heights, widths, and/or other characteristics of MTJ stacks.

In many processor-based systems, different memory applications can beprovided. For example, cache memory can be provided to store data thatis frequently accessed by a processor during operation. Main memory canbe provided to store data that is accessed less often than data in cachememory, but more often than data in long-term memory. Long-term memorycan be provided to store large amounts of data that are accessed lessoften than data in main memory. Since the data stored in each of thesememory applications are accessed at varying frequencies, each memoryapplication can have different access times requirements. For example,cache memory can be required to have faster access times than mainmemory because providing faster access times in cache memory canincrease device speed to a greater extent than providing faster accesstimes in main memory. Long-term memory access times can have evenfurther reduced access times requirements for a similar reason. It wouldbe desirable to use MRAM as the type of memory for all of these memoryapplications because MRAM has high data retention rates and consumes alow amount of power.

For example, eFlash memory, cache memory, and main memory using MRAM bitcells in MRAM arrays may be required on a single semiconductor die. Inusing MRAM for different memory applications, it is desirable to havehigh data retention rates and fast access times because high dataretention rates increase device reliability and fast access timesincrease device speed. For example, for cache memory, reducing accesstimes can be favored over increasing retention rates because the maingoal of cache memory can be to enable high-speed processing. Inlong-term memory, such as eFlash memory for example, increasingretention rates can be favored over reducing access times because themain goal of eFlash can be to provide long-term reliable data storage.Main memory can favor performance specifications between those requiredfor cache memory and those required for eFlash memory because mainmemory can be used as intermediate memory between long-term memory andcache memory.

However, in MRAM, increasing the retention rate can come at the expenseof slowing down access times. Conversely, reducing the retention rate inMRAM can allow for faster access times. This is because retention ratesand access times of an MTJ in an MRAM bit cell are based on an energybarrier of the MTJ. An energy barrier of an MTJ is an amount of energyrequired to change a magnetic orientation of a free layer of the MTJ.Factors that affect the energy barrier of an MTJ include widths and/ormaterial types of the various layers of an MTJ. Increasing an energybarrier of an MTJ makes the MTJ more resilient to external effects suchas temperature variation, leakage current, and stray capacitance,because such external effects must transfer a higher amount of energy tochange the magnetic orientation of a free layer of the MTJ. However,increasing the energy barrier of the MTJ slows access times because awrite current, for example, must transfer a higher amount of energy tothe free layer of the MTJ, which requires a longer period of time at afixed voltage. Therefore, although it is desirable to have high dataretention rates and fast access times in MRAM, tradeoffs must be madebetween retention rates and access times.

In many applications, such as system-on-a-chip (SoC) devices, differenttypes of memory requiring different performance specifications may berequired in a memory system on a single semiconductor die. For example,it may be desired to use MRAM for eFlash memory, cache memory, and mainmemory on a single semiconductor die, because MRAM has high dataretention rates and consumes a low amount of power. In this regard, FIG.2A illustrates a top view of an exemplary semiconductor die 200 thatincludes a plurality of MRAM arrays 208(1)-208(L) along an A-A line forsupporting memory applications. In this example, three (3) MRAM arrays208(1)-208(3) are provided in the semiconductor die 200. In someaspects, the semiconductor die 200 in FIG. 2A can be a semiconductor dieof an SoC. Each MRAM array 208(1)-208(3) in FIG. 2A can be used for adifferent type of memory if desired. In this example, the first MRAMarray 208(1) can be used for eFlash memory, the second MRAM array 208(2)can be used for main memory (embedded dynamic random access memory(eDRAM)), and the third MRAM array 208(3) can be used for embeddedstatic random access memory (eSRAM) cache memory. Each MRAM array208(1)-208(3) in FIG. 2A includes a respective plurality of MRAM bitcells 201(1)-201(3) and each MRAM bit cell 201(1)(1)-201(1)(M),201(2)(1)-201(2)(N), 201(3)(1)-201(3)(P) includes an MTJ 202 having anMTJ stack 204 between a top electrode layer 209 and a bottom electrodelayer 210. Each MTJ stack 204 is formed in a metal layer 206 andincludes a free layer 211, a pinned layer 213, and a tunnel barrierlayer 212. A magnetic moment M_(FL) of the free layer 211 can bechanged, but a magnetic moment M_(PL) of the pinned layer 213 remainsfixed or “pinned.” Each MTJ stack 204 is configured to store dataaccording to the magnetic moment M_(FL) of its free layer 211 as beingeither parallel (P) or anti-parallel (AP) to the magnetic moment M_(PL)of its pinned layer 213 to represent different memory states (i.e., alogical ‘1’ or ‘0’).

The MRAM bit cells 201(1)(1)-201(3)(P) provided in the MRAM arrays208(1)-208(3) may require different access times based on their memoryapplication. For example, the third plurality of MRAM bit cells 201(3)in the third MRAM array 208(3) used for eSRAM cache memory, for example,may require faster access times than the first plurality of MRAM bitcells 201(1) in the first MRAM array 208(1) used for eFlash memory,because eSRAM cache memory is used in high-speed processing more oftenthan eFlash memory. Thus, lower data retention rates might be anacceptable tradeoff to provide faster access times for the MRAM bitcells 201(3)(1)-201(3)(P) in the third MRAM array 208(3) used for cachememory. Conversely, the first plurality of MRAM bit cells201(1)(1)-201(1)(M) in the first MRAM array 208(1) used for eFlashmemory may require higher data retention rates than the third pluralityof MRAM bit cells 201(3) in the third MRAM array 208(3) used for cachememory, because eFlash memory is used in long-term memory requiringincreased reliability more often than cache memory. Main memory (eDRAM)may require higher data retention rates than cache memory, but may alsorequire faster access times than eFlash memory. This is because mainmemory (eDRAM) is often used as intermediate memory between long-termmemory and cache memory (eSRAM). In this manner, the second plurality ofMRAM bit cells 201(2) in the second MRAM array 208(2) used for mainmemory (eDRAM) may require performance specifications between thoserequired for the first plurality of MRAM bit cells 201(1) in the firstMRAM array 208(1) used for eFlash memory and those required for thethird plurality of MRAM bit cells 201(3) in the third MRAM array 208(3)used for cache memory (eSRAM). Thus, for applications requiringdifferent types of memory using MRAM on a semiconductor die, it may bedesirable to provide MRAM bit cells in MRAM arrays having varyingperformance specifications on a single semiconductor die.

In examples discussed below, the MRAM bit cells 201(1)(1)-201(3)(P) inthe MRAM arrays 208(1)-208(3) are fabricated to have varying performancespecifications in the semiconductor die 200 by varying energy barriersof the MTJs 202(1)-202(3) in the MRAM bit cells 201(1)(1)-201(3)(P). Forexample, FIG. 2B illustrates a cross-sectional side view of FIG. 2Aalong the cross-section A-A and between break lines in each MRAM array208(1)-208(3), 208(L). In this regard, FIG. 2B illustrates exemplaryfirst, second, and third MTJs 202(1)-202(3) in respective first, second,and third MRAM bit cells 201(1)(1), 201(2)(1), 201(3)(1) in respectivefirst, second, and third pluralities of MRAM bit cells 201(1)-201(3),respectively. FIG. 2B illustrates one MRAM bit cell 201(1)(1)-201(3)(1)for each of the first, second, and third pluralities of MRAM bit cells201(1)-201(3). Each MRAM bit cell 201(1)(1)-201(3)(1) illustrated inFIG. 2B represents each and every MRAM bit cell 201(1)(1)-201(3)(P) inthe respective plurality of MRAM bit cells 201(1)-201(3) that can bedisposed left and right of the MRAM bit cell 201(1)(1)-201(3)(1) in theX-axis direction and in front and behind in the Z-axis direction. Asdiscussed below, including MRAM bit cells having vary performancespecifications on the same semiconductor die allows MRAM to be used fordifferent memory applications. In this manner, MRAM bit cells in MRAMarrays can provide varying performance specifications for differentmemory applications while also gaining the benefits of higher dataretention and lower power consumption associated with MRAM.

In this regard, each MTJ 202(1)-202(3) in FIG. 2B includes an MTJ stack204(1)-204(3) having an energy barrier E_(b(1))-E_(b(3)) according toits material composition and geometry. As shown in FIG. 2B, each MTJstack 204(1)-204(3) is between a top electrode layer 209(1)-209(3) and abottom electrode layer 210(1)-210(3), and includes a tunnel barrierlayer 212(1)-212(3) between a free layer 211(1)-211(3) and a pinnedlayer 213(1)-213(3). As discussed above, the energy barrierE_(b(1))-E_(b(3)) of each MTJ 202(1)-202(3) is an amount of energyrequired to substantially invert a direction of a magnetic momentM_(FL(1))-M_(FL(3)) of its free layer 211(1)-211(3) relative to amagnetic moment M_(PL(1))-M_(PL(3)) of its pinned layer 213(1)-213(3).For example, the material compositions and/or the widths W₁-W₃ of theMTJ stacks 204(1)-204(3) in FIG. 2B can be different to vary the energybarriers E_(b(1))-E_(b(3)) of each MTJ 202(1)-202(3). For example, thefirst MTJ 202(1) and the second MTJ 202(2) have material compositionsand widths W₁, W₂ such that the first energy barrier E_(b(1)) is higherthan the second energy barrier E_(b(2)). Similarly, the third MTJ 202(3)has a material composition and width W₃ such that the second energybarrier E_(b(2)) is higher than the third energy barrier E_(b(3)). Inthis manner, the first, second, and third MTJs 202(1)-202(3) are able toprovide MRAM arrays 208(1)-208(3) having varying performancespecifications for different memory types in the semiconductor die 200,if desired.

In this example, and as will be discussed in more detail below, the MRAMarrays 208(1)-208(3) having MRAM bit cells 201(1)(1)-201(3)(P) withvarying energy barriers E_(b(1))-E_(b(3)) to vary performancespecifications are also fabricated in a same layer of the semiconductordie 200 to avoid fabricating the MRAM arrays 208(1)-208(3) in differentlayers to avoid increasing the height of the semiconductor die 200 inthe Y-axis direction. In this regard, each MTJ 202(1)-202(3) in FIG. 2Bis formed over a respective bottom interconnect 214(1)-214(3) formed inan interconnect layer 216 of the semiconductor die 200 in the Y-axisdirection. In this example, each bottom interconnect 214(1)-214(3)includes a first bottom via 218(1)-218(3) (i.e., a first via, a secondvia, and a third via), a bottom metal line 220(1)-220(3), and a secondbottom via 222(1)-222(3). Each first bottom via 218(1)-218(3) is formedin a diffusion barrier layer 224 of the interconnect layer 216. Eachbottom metal line 220(1)-220(3) is formed above a respective secondbottom via 222(1)-222(3) in an inter-metal layer 226 of the interconnectlayer 216. Each bottom interconnect 214(1)-214(3) is coupled to anaccess transistor 228(1)-228(3) formed in a semiconductor layer 230 ofthe semiconductor die 200 to control current to the MTJ 202(1)-202(3)during read/write operations. Each access transistor 228(1)-228(3)includes a respective gate G₁-G₃, source S₁-S₃, and drain D₁-D₃. In thisexample, each bottom interconnect 214(1)-214(3) is coupled to arespective drain D₁-D₃ of each access transistor 228(1)-228(3). A wordline WL₁-WL₃ of each access transistor 228(1)-228(3) is coupled to arespective gate G₁-G₃ of each access transistor 228(1)-228(3). Thesource S₁-S₃ of each access transistor 228(1)-228(3) is coupled to avoltage source V_(S(1))-V_(S(3)) through a respective source lineSL₁-SL₃ of each access transistor 228(1)-228(3).

When reading or writing data to each MTJ 202(1)-202(3), the gate G₁-G₃of the respective access transistor 228(1)-228(3) is activated byactivating the respective associated word line WL₁-WL₃. In a writeoperation, for example, a write current is generated between the drainD₁-D₃ and the source S₁-S₃ of each access transistor 228(1)-228(3) andacross each MTJ 202(1)-202(3). If the magnetic momentM_(FL(1))-M_(FL(3)) of each free layer 211(1)-211(3) of each MTJ202(1)-202(3) is to be changed from AP to P, a write current flowingfrom each free layer 211(1)-211(3) to each respective pinned layer213(1)-213(3) is generated. If the magnetic moment M_(FL(1))-M_(FL(3))of each free layer 211(1)-211(3) of each MTJ 202(1)-202(3) is to bechanged from P to AP relative to the respective pinned layer213(1)-213(3), a write current flowing from each pinned layer213(1)-213(3) to each respective free layer 211(1)-211(3) is generated.Thus, in this manner, each access transistor 228(1)-228(3) controls theread/write current across each respective MTJ 202(1)-202(3).

A read operation is different from a write operation in that the amountof current necessary to perform a write operation is higher than theamount of current necessary to perform a read operation. As noted above,a higher current transfers a higher amount of energy to a free layer ofthe MTJ. If one MTJ has a higher energy barrier than another MTJ, thenthe MTJ with the higher energy barrier can require a higher writecurrent to perform a write operation on the MTJ. For example, performinga write operation on the first MTJ 202(1) in FIG. 2B having the firstenergy barrier E_(b(1)) requires a higher write current than performinga write operation on the third MTJ 202(3) having the third energybarrier E_(b(3)) lower than the first energy barrier E_(b(1)). In thismanner, the MTJs 202(1)-202(3) having higher energy barriersE_(b(1))-E_(b(3)) can require higher write currents to perform writeoperations on the respective MTJs 202(1)-202(3).

Factors that affect the energy barriers E_(b(1))-E_(b(3)) of the MTJs202(1)-202(3) include the material(s) used to form the MTJ stacks204(1)-204(3) as well as heights H₁-H₃ and widths W₁-W₃ of the layers inthe MTJ stacks 204(1)-204(3). The materials used to form the MTJ stacks204(1)-204(3) influence the respective energy barriers E_(b(1))-E_(b(3))because the energy barriers E_(b(1))-E_(b(3)) of the respective MTJstacks 204(1)-204(3) are associated with resistances of the respectiveMTJ stacks 204(1)-204(3). By fabricating the MTJ stacks 204(1)-204(3)from strong free layer magnetic moment materials, the MTJ stacks204(1)-204(3) can have higher energy barriers E_(b(1))-E_(b(3)). Forexample, forming the first free layer 211(1) of the first MTJ 202(1)from a first material can result in the first MTJ 202(1) having thefirst energy barrier E_(b(1)). Similarly, forming the second free layer211(2) of the second MTJ 202(2) from a second material can result in thesecond MTJ 202(2) having the second energy barrier E_(b(2)) differentfrom the first energy barrier E_(b(1)). If the first energy barrierE_(b(1)) is greater than the second energy barrier E_(b(2)), then thefirst MTJ 202(1) may have a higher data retention rate and a slowerswitching speed than the second MTJ 202(2). In this manner, thematerials used to form the layers of the MTJ stacks 204(1)-204(3) caninfluence the energy barriers E_(b(1))-E_(b(3)) of the MTJs202(1)-202(3), and thus the performance specifications of the MTJs202(1)-202(3).

The heights H₁-H₃ and widths W₁-W₃ of the layers in the MTJ stacks204(1)-204(3) can also influence the energy barriers E_(b(1))-E_(b(3))of the MTJ stacks 204(1)-204(3). For example, forming the first freelayer 211(1) of the first MTJ 202(1) to a first width W₁ can result inthe first MTJ 202(1) having the first energy barrier E_(b(1)).Similarly, forming the second free layer 211(2) of the second MTJ 202(2)to a second width W₂ can result in the second MTJ 202(2) having thesecond energy barrier E_(b(2)) different from the first energy barrierE_(b(1)). Similar to the discussion above, if the first energy barrierE_(b(1)) is greater than the second energy barrier E_(b(2)), then thefirst MTJ 202(1) may have a higher data retention rate and a slowerswitching speed than the second MTJ 202(2). In this manner, the widthsW₁-W₃ of the layers of the MTJ stacks 204(1)-204(3) can influence theenergy barriers E_(b(1))-E_(b(3)) of the respective MTJs 202(1)-202(3),and thus the performance specifications of the MTJs 202(1)-202(3).

As discussed above, to vary the energy barriers E_(b(1))-E_(b(3)) amongthe MRAM bit cells 201(1)(1)-201(3)(P), the MTJ stacks 204(1)-204(3) canbe formed from different material compositions that can affect theenergy barriers E_(b(1))-E_(b(3)) of the MTJs 202(1)-202(3). Forexample, the bottom electrode layer 210(1)-210(3) of each MTJ202(1)-202(3) can include materials such as tantalum (Ta), tantalum (Ta)nitride (N) (TaN), tungsten (W), copper (Cu)-based materials, Ruthenium(Ru), platinum (Pt), Hafnium (Hf) iridide (Ir) (HfIr), Terbium(Tb)-Cobalt (Co)-Iron (Fe) (TbCoFe), and/or TbWFe, as non-limitingexamples. The bottom electrode layer 210(1)-210(3) of each MTJ202(1)-202(3) can include a thickness in the range of approximately 5-20nanometers (nm), as non-limiting examples. The top electrode layer209(1)-209(3) of each MTJ 202(1)-202(3) can include materials such asTa, TaN, titanium (Ti), titanium nitride (TiN), Ru, W, Pt, HfIr, TbCoFe,and/or TbWFe, as non-limiting examples. The top electrode layer209(1)-209(3) of each MTJ 202(1)-202(3) can include a thickness in therange of approximately 15-80 nm, as a non-limiting example.

Similarly, the free layers 211(1)-211(3) of the MTJ stacks 204(1)-204(3)can be formed from different material compositions that can affect theenergy barriers E_(b(1))-E_(b(3)) of the MTJs 202(1)-202(3). An energybarrier of an MTJ can be determined by calculating the effectiveanisotropy energy constant (K_(eff)) of the MTJ, which is equal to theanisotropy field (H_(k)) times one-half the saturation magnetization(M_(s)). Since the anisotropy field (H_(k)) and the saturationmagnetization (M_(s)) can both be measured, the effective anisotropyenergy constant (K_(eff)) can be calculated using the equation,K_(eff)=H_(k)*M_(s)/2. Once the effective anisotropy energy constant(K_(eff)) is calculated, the energy barrier E_(b) can be calculatedusing the equation, E_(b)=(K_(eff)*V)/(K_(B)*T), where V is the volumeof the free layer, T is temperature, and K_(B) is the Bohr magneton.Aspects disclosed herein can include, for a CoFeB-based free layer, ananisotropy field (H_(k)) between approximately 2000-5000 Oersteds (Oe),and a saturation magnetization (M_(s)) between approximately 300-1300emu/cc. In at least one example, for the first free layer 211(1) of thefirst MTJ 202(1), materials can include Co, Fe, B, and CoFeB-basedmaterials. In this manner, having the first MTJ 202(1) used for eFlashmemory, for example, can include having a high K_(eff) such that H_(k)is greater than 3500 Oe and M_(s) is greater than 800 emu/cc. The secondfree layer 211(2) of the second MTJ 202(2) can include materials such asCo, Fe, B, and CoFeB-based materials. In this regard, having the secondMTJ 202(2) used for main memory (eDRAM), for example, can include havinga K_(eff) such that H_(k) is approximately equal to 3000 Oe and M_(s) isapproximately between 600-800 emu/cc. The third free layer 211(3) of thethird MTJ 202(3) can include materials such as Co, Fe, B, andCoFeB-based materials. In this regard, having the third MTJ 202(3) usedfor eSRAM cache memory, for example, can include having a K_(eff) suchthat H_(k) is approximately less than 2500 Oe and M_(s) is approximatelyless than 600 emu/cc.

Similarly, to vary the energy barriers E_(b(1))-E_(b(3)) between theMRAM bit cells 201(1)(1)-201(3)(P), the pinned layers 213(1)-213(3) ofthe MTJ stacks 204(1)-204(3) can be formed from different materialcompositions that can affect the energy barriers E_(b(1))-E_(b(3)) ofthe MTJs 202(1)-202(3). For example, the first pinned layer 213(1) ofthe first MTJ 202(1) can include materials such as Co, Pt, Co/Pt-basedmaterials, B, and/or CoFeB-based materials. The second pinned layer213(2) of the second MTJ 202(2) can include materials such as Co, Nickel(Ni), Co/Ni-based materials, Pt, Co/Pt-based materials, B, and/orCoFeB-based materials. The third pinned layer 213(3) of the third MTJ202(3) can include materials such as Co, Ni, CoNi-based materials, Fe,B, and/or CoFeB-based materials.

Similarly, to vary the energy barriers E_(b(1))-E_(b(3)) among the MRAMbit cells 201(1)(1)-201(3)(P), the tunnel barrier layers 212(1)-212(3)of the MTJ stacks 204(1)-204(3) can be formed from different materialcompositions that can affect the energy barriers E_(b(1))-E_(b(3)) ofthe MTJs 202(1)-202(3). For example, the first tunnel barrier layer212(1) can include resistance area products (RAs) such as approximately8-10 ohm-micrometers squared (Ωμm²) and tunnel magnetoresistances (TMRs)approximately 150%. The second tunnel barrier layer 212(2) can includeRAs such as approximately 5-8 Ωμm² and TMRs approximately 200%. Thethird tunnel barrier layer 212(3) can include RAs such as less than 5Ωμm² and TMRs approximately 200%.

Critical dimensions of the first MTJ 202(1) can include criticaldimensions greater than seventy (70) nm. Critical dimensions of thesecond MTJ 202(2) can include critical dimensions between approximatelythirty-five (35) and seventy (70) nm. Critical dimensions of the thirdMTJ 202(3) can include critical dimensions less than thirty-five (35)nm. Retention rates of the first MTJ 202(1) can include ten (10) yearsat one hundred twenty-five (125) degrees Celsius (C). Retention rates ofthe second MTJ 202(2) can include ten (10) years at eighty-five (85)degrees Celsius (C). Retention rates of the third MTJ 202(3) can includea few days or months at eighty-five (85) degrees Celsius (C). Energybarriers E_(b(1))-E_(b(3)) can be in the range of approximately 80-100electronvolts (eV) for eFlash, approximately 50-60 eV for eSRAM, andapproximately 60-70 eV for eDRAM, as non-limiting examples. MTJ stacks204(1)-204(3) can have heights between approximately 15-80 nm, asnon-limiting examples. Pinned layers 213(1)-213(3) for eFlash caninclude Co/Pt-based materials for a multilayer (ML) and CoFeB-basedmaterials for a synthetic antiferromagnetic (SAF) layer. Pinned layers213(1)-213(3) for eDRAM can include Co/Pt-based materials for a ML andCoFeB-based materials for an SAF layer. Pinned layers 213(1)-213(3) foreSRAM for cache memory can include Co/Ni-based materials for a ML andCoFeB-based materials for an SAF layer, as non-limiting examples. Eachaccess transistor 228(1)-228(3) can be a planar n-type metal-oxidesemiconductor (MOS) (NMOS) or p-type MOS (PMOS) type transistor, an NMOSor PMOS Fin field-effect transistor (FinFET), or a silicon-on-insulator(SOI) NMOS or PMOS type transistor, as non-limiting examples. Each firstbottom via 218(1)-218(3) can include materials such as Ta, TaN, W, andCu-based materials, such that each first bottom via 218(1)-218(3) canhave heights between approximately 5-20 nm, and widths larger or smallerthan the width of each MTJ 202(1)-202(3), as non-limiting examples. Eachsecond bottom via 222(1)-222(3) can include materials such as Cu, W, Ta,and/or Ta/TaN, and have heights between approximately 50-100 nm, asnon-limiting examples. Each bottom metal line 220(1)-220(3) can includematerials such as Cu, W, and/or Ta/TaN, and have heights betweenapproximately 50-100 nm and widths between approximately 30-100 nm, asnon-limiting examples. The diffusion barrier layer 224 can includematerials such as silicon nitride (SiN), SiCON, and/or siliconoxynitride (SiON), and have heights such as approximately 10-30 nm, asnon-limiting examples. The inter-metal layer 226 can include materialssuch as silicon dioxide (SiO2), SiON, and/or SiN, and have heightsbetween approximately 50-100 nm, as non-limiting examples.

In FIG. 2B, the MTJs 202(1)-202(3) having different energy barriersE_(b(1))-E_(b(3)) are fabricated in the same layer of the semiconductordie 200 to avoid having to provide additional layers in thesemiconductor die 200 for the different MTJs 202(1)-202(3). Fabricatingthe MTJs 202(1)-202(3) having different energy barriersE_(b(1))-E_(b(3)) in the same layer of a semiconductor die 200 canreduce the overall height of the semiconductor die 200, thereby reducingthe overall size of the semiconductor die 200. In this regard, FIG. 3illustrates an exemplary fabrication process 300 employed to fabricatethe three (3) MTJ stacks 204(1)-204(3) in the semiconductor die 200 inFIG. 2B. FIGS. 4A-4S illustrate various fabrication stages of theexemplary fabrication process 300 employed to fabricate the three (3)MTJ stacks 204(1)-204(3) in the semiconductor die 200 in FIG. 2B. Theexemplary fabrication process 300 in FIG. 3 will be discussed inconjunction with the exemplary process steps in FIGS. 4A-4S.

In this regard, a first step of the fabrication process 300 in FIG. 3includes forming a first blocking layer 432(1) over the second bottominterconnect 214(2) of the second MRAM array 208(2), wherein the secondbottom interconnect 214(2) is in the interconnect layer 216 of thesemiconductor die 200 (block 302 in FIG. 3). In this regard, FIGS. 4A-4Cillustrate cross-sectional views of first, second, and third fabricationstages 400(1)-400(3) of forming the first blocking layer 432(1) over thesecond bottom interconnect 214(2) of the second MRAM array 208(2)according to the fabrication step in block 302 in FIG. 3. As shown inFIGS. 4A-4C, the first blocking layer 432(1) is formed over the secondbottom interconnect 214(2) in the Y-axis direction to protect the secondbottom interconnect 214(2) while depositing a first MTJ film stack436(1) in a later step. In FIGS. 4A and 4B, a bottom electrode film 434is formed in the interconnect layer 216 above the diffusion barrierlayer 224 and each first bottom via 218(1)-218(3). FIG. 4C illustratesforming the first blocking layer 432(1) over the second bottominterconnect 214(2) of the second MRAM array 208(2) and the third bottominterconnect 214(3) of the third MRAM array 208(3). In this example, afirst photoresist mask 438(1) is used to form the first blocking layer432(1). In this manner, the first blocking layer 432(1) is formed overthe second bottom interconnect 214(2) of the second MRAM array 208(2)and the third bottom interconnect 214(3) of the third MRAM array 208(3).

The semiconductor die 200 can be provided by processes such as chemicalvapor deposition (CVD), physical vapor deposition (PVD),photolithography, reactive ion etching (RIE), etch, chemical mechanicalplanarization (CMP), and/or wet/dry cleaning processes, as non-limitingexamples. The semiconductor layer 230 can comprise materials such as Si,SiO, a high-k oxide material, a metal gate material, B, phosphorous (P),arsenic (As), Ti, Co, Ni, and/or silicon germanium (SiGe), asnon-limiting examples. The voltage source V_(S(1))-V_(S(3)) of eachaccess transistor 228(1)-228(3) can be a single voltage source or somecombination of different voltage sources, and can provide voltages inthe range of approximately 0.5-1.8 volts (V), as non-limiting examples.The bottom electrode film 434 can comprise materials including Ta, TaN,W, Cu, Ru, Ti, and/or TiN, and can have heights between approximately10-20 nm, as non-limiting examples. The bottom electrode film 434 can bedeposited using a process such as PVD, as a non-limiting example. Thefirst blocking layer 432(1) can comprise materials such as SiO2, SiN,and/or SiCON, and can be formed using a process such as CVD, as anon-limiting example. The first photoresist mask 438(1) can be depositedusing processes such as spin coating, as a non-limiting example.

Once the first blocking layer 432(1) is formed over the second bottominterconnect 214(2) in the Y-axis direction, the first MTJ stack film436(1) can be deposited so as to later form the first MTJ stack 204(1)from the first MTJ stack film 436(1). The fabrication process 300 inFIG. 3 includes depositing a first MTJ stack film 436(1) over the firstbottom interconnect 214(1) of the first MRAM array 208(1) and at least aportion of the first blocking layer 432(1), wherein the first bottominterconnect 214(1) is in the interconnect layer 216 of thesemiconductor die 200 (block 304 in FIG. 3). In this regard, FIG. 4Dillustrates a cross-sectional view of a fourth fabrication stage 400(4)of depositing the first MTJ stack film 436(1) over the first bottominterconnect 214(1) of the first MRAM array 208(1) and at least aportion of the first blocking layer 432(1) according to the fabricationstep in block 304 in FIG. 3. Further, the fabrication process 300 inFIG. 3 includes depositing a first top electrode film 433(1) over thefirst MTJ stack film 436(1) (block 306 in FIG. 3), as illustrated in thefourth fabrication stage 400(4) in FIG. 4D. As shown in FIG. 4D,depositing the first MTJ stack film 436(1) includes depositing a firstfree film 439(1), a first tunnel barrier film 440(1), and a first pinnedfilm 441(1). In this example, the first MTJ stack film 436(1) isdeposited conformally over the bottom electrode film 434 in the firstMRAM array 208(1) and over the first blocking layer 432(1) in the secondMRAM array 208(2) and the third MRAM array 208(3). The first MTJ stackfilm 436(1) can be formed by a process such as PVD, and can comprisematerials such as Ta/TaN, Co, Pt, platinum manganese (PtMn), CoFe,CoFeB, magnesium oxide (MgO), Ru, and/or HfIr, Ta, as non-limitingexamples. For the varying memory applications in the examples above, thepinned layers 213(1)-213(3) of the MTJs 202(1)-202(3) should be of thesame material. For eFlash memory applications, the free layer211(1)-211(3) can be Fe-rich (i.e., the material is more than 50% Fe)and/or include a CoFeB/Fe-rich alloy. For example, Co10Fe70B20 can beused as a material for the free layer 211(1)-211(3) of each MTJ202(1)-202(3). For eDRAM memory applications, composite Fe-rich alloysand/or CoFeB can be used as materials for the free layer. In thisexample, the free layer 211(1)-211(3) implemented in an eDRAM memoryapplication can be thinner than the free layer 211(1)-211(3) implementedin an eFlash memory application. For eSRAM memory applications, the freelayer 211(1)-211(3) can be thinner than the free layer 211(1)-211(3)used in the exemplary eDRAM memory applications, as discussed above. Thefree layer 211(1)-211(3) in eDRAM memory applications can be made ofCoFeB, for example, and doped with Ta, for example. Each of these memoryapplications discussed above can be fabricated using a process such asPVD. Additionally, the first top electrode film 433(1) can be formed bya process such as PVD, and can comprise materials such as Ta, TaN, Ru,Ti, TiN, and/or W, as non-limiting examples.

Once the first MTJ film stack 436(1) is deposited, a first mask, whichis first hard mask 442(1) in this example, can be deposited over aportion of the first MTJ film stack 436(1) in the Y-axis direction in alater step to protect that portion while another portion is removed. Thefabrication process 300 in FIG. 3 also includes depositing the firsthard mask 442(1) over a portion of the first top electrode film 433(1)over the first MTJ stack film 436(1) over the first bottom interconnect214(1) (block 308 in FIG. 3). In this regard, FIG. 4E illustrates across-sectional view of a fifth fabrication stage 400(5) of depositingthe first hard mask 442(1) over a portion of the first top electrodefilm 433(1) according to the fabrication step in block 308 in FIG. 3. Asshown in FIG. 4E, the first hard mask 442(1) is deposited over theportion of the first top electrode film 433(1) over the first MTJ stackfilm 436(1) over the first bottom interconnect 214(1). In this manner,the first hard mask 442(1) covers the portion of the first top electrodefilm 433(1) above the first bottom interconnect 214(1), protecting aportion of the first top electrode film 433(1) and a portion of thefirst MTJ stack film 436(1) thereunder from etching, as will bediscussed in further detail below. The first hard mask 442(1) can bedeposited using a process such as CVD, as a non-limiting example, andcan comprise materials such as SiO2, silicon nitride (SiNx), and/orSiCN, as non-limiting examples.

The fabrication process 300 in FIG. 3 also includes removing a portionof the first top electrode film 433(1) and a portion of the first MTJstack film 436(1) not under the first hard mask 442(1) to form the firsttop electrode layer 209(1) over the first MTJ stack 204(1) over thefirst bottom interconnect 214(1) of the first MRAM array 208(1) (block310 in FIG. 3). In this regard, FIG. 4F illustrates a cross-sectionalview of a sixth fabrication stage 400(6) of removing a portion of thefirst top electrode film 433(1) and a portion of the first MTJ stackfilm 436(1) not under the first hard mask 442(1) according to thefabrication step in block 310 in FIG. 3. Forming the first top electrodelayer 209(1) over the first MTJ stack 204(1) over the first bottominterconnect 214(1) of the first MRAM array 208(1) in the Y-axisdirection is illustrated in a later step. In this regard, a portion ofthe first top electrode film 433(1) and a portion of the first MTJ stackfilm 436(1) not covered by the first hard mask 442(1) are removed. Thefirst blocking layer 432(1) is not removed as it is used in this exampleto cover and protect the second bottom interconnect 214(2) and the thirdbottom interconnect 214(3). In this example, removing may includeprocesses such as etching, plasma chemical etching, ion miller physicaletching, and/or cleaning processes, as non-limiting examples. Etchantsmay include tetrafluoromethane (CF4), C12SF6 octafluorocyclobutane(C4F8), and/or fluoroform (CHF3), as non-limiting examples.

The fabrication process 300 in FIG. 3 also includes removing at least aportion of the first blocking layer 432(1) over the second bottominterconnect 214(2) of the second MRAM array 208(2) (block 312 in FIG.3). In this regard, FIGS. 4G-4H illustrate cross-sectional views ofseventh and eighth fabrication stages 400(7), 400(8) of removing atleast a portion of the first blocking layer 432(1) over the secondbottom interconnect 214(2) of the second MRAM array 208(2) in the Y-axisdirection according to the fabrication step in block 312 in FIG. 3. Inthis regard, FIG. 4G illustrates removing the first hard mask 442(1) andforming a second blocking layer 432(2) over the second bottominterconnect 214(2), the third bottom interconnect 214(3), and the firsttop electrode film 433(1). In this example, the second blocking layer432(2) is formed over the first blocking layer 432(1) and the first topelectrode film 433(1) to protect a portion of the first top electrodefilm 433(1) and a portion of the first MTJ stack film 436(1) thereunderfrom etching, as will be discussed in further detail below. FIG. 4Hillustrates removing a portion of the first blocking layer 432(1) and aportion of the second blocking layer 432(2) to expose the second bottominterconnect 214(2) of the second MRAM array 208(2). In this example, asecond photoresist mask 438(2) is used to expose the portion of thefirst blocking layer 432(1) to be removed. In this manner, a second MTJstack film 436(2) may be deposited above the exposed second bottominterconnect 214(2) in a later step. In alternative methods, instead offorming the second blocking layer 432(2) over the first blocking layer432(1), the first blocking layer 432(1) can be removed and the secondblocking layer 432(2) can be deposited thereafter. However, thisalternative method may not be desirable because removing the firstblocking layer 432(1) may damage the bottom electrode film 434 throughmechanisms such as oxidative damage. The second photoresist mask 438(2)can comprise materials such as photopolymeric, photodecomposing, andphotocross-slinking photoresist materials, and can be deposited usingprocesses such as spin coating, as non-limiting examples.

The fabrication process 300 in FIG. 3 includes depositing the second MTJstack film 436(2) over the second bottom interconnect 214(2) of thesecond MRAM array 208(2) (block 314 in FIG. 3). In this regard, FIG. 4Iillustrates a cross-sectional view of a ninth fabrication stage 400(9)of depositing a second MTJ stack film 436(2) in the Y-axis directionover the second bottom interconnect 214(2) of the second MRAM array208(2) and at least a portion of the second blocking layer 432(2)according to the fabrication step in block 314 in FIG. 3. Further, thefabrication process 300 in FIG. 3 also includes depositing a second topelectrode film 433(2) over the second MTJ stack film 436(2) (block 316in FIG. 3). In this regard, the fabrication process 300 in FIG. 3includes depositing the second top electrode film 433(2) over the secondMTJ stack film 436(2) as illustrated in the ninth fabrication stage400(9) in FIG. 4I. As shown in FIG. 4I, depositing the second MTJ stackfilm 436(2) includes depositing a second free film 439(2), a secondtunnel barrier film 440(2), and a second pinned film 441(2). In thisexample, the second MTJ stack film 436(2) is deposited conformally overthe bottom electrode film 434 in the second MRAM array 208(2) and overthe second blocking layer 432(2) in the first MRAM array 208(1) and thethird MRAM array 208(3). The second MTJ stack film 436(2) can be formedby a process such as PVD, as a non-limiting example. Additionally, thesecond top electrode film 433(2) can be formed by a process such as PVD,as a non-limiting example.

The fabrication process 300 in FIG. 3 also includes depositing a secondmask, which is second hard mask 442(2) in this example, over a portionof the second top electrode film 433(2) over the second MTJ stack film436(2) over the second bottom interconnect 214(2) (block 318 in FIG. 3).In this regard, FIG. 4J illustrates a cross-sectional view of a tenthfabrication stage 400(10) of depositing the second hard mask 442(2) inthe Y-axis direction over a portion of the second top electrode film433(2) according to the fabrication step in block 318 in FIG. 3. Asshown in FIG. 4J, the second hard mask 442(2) is deposited over theportion of the second top electrode film 433(2) over the second MTJstack film 436(2) over the second bottom interconnect 214(2). In thismanner, the second hard mask 442(2) covers the portion of the second topelectrode film 433(2) above the second bottom interconnect 214(2),protecting the portion of the second top electrode film 433(2) and aportion of the second MTJ stack film 436(2) thereunder from etching, aswill be discussed in further detail below. The second hard mask 442(2)can be deposited using processes such as CVD or PVD and can comprisematerials such as SiO2, SiNx, and/or SiCN, as non-limiting examples.

The fabrication process 300 in FIG. 3 also includes removing a portionof the second top electrode film 433(2) and a portion of the second MTJstack film 436(2) not under the second hard mask 442(2) to form thesecond top electrode layer 209(2) over the second MTJ stack 204(2) overthe second bottom interconnect 214(2) of the second MRAM array 208(2)(block 320 in FIG. 3). In this regard, FIG. 4K illustrates across-sectional view of an eleventh fabrication stage 400(11) ofremoving a portion of the second top electrode film 433(2) and a portionof the second MTJ stack film 436(2) not under the second hard mask442(2) according to the fabrication step in block 320 in FIG. 3. Formingthe second top electrode layer 209(2) over the second MTJ stack 204(2)over the second bottom interconnect 214(2) of the second MRAM array208(2) is shown in a later step. In this regard, a portion of the secondtop electrode film 433(2) and a portion of the second MTJ stack film436(2) not covered by the second hard mask 442(2) are removed. Thesecond blocking layer 432(2) is not removed as it is used in thisexample to cover and protect the first top electrode film 433(1), thefirst MTJ stack film 436(1), and the third bottom interconnect 214(3).In this example, removal may include processes such as etching, ionmiller physical etching, plasma chemical etching, and/or cleaningprocesses, as non-limiting examples. Etchants may include CF4, C12SF6C4F8, and/or CHF3, as non-limiting examples.

FIGS. 4L-4M illustrate cross-sectional views of twelfth and thirteenthfabrication stages 400(12), 400(13) of depositing a third blocking layer432(3) and removing at least a portion of the third blocking layer432(3) over the third bottom interconnect 214(3) of the third MRAM array208(3). In this regard, FIG. 4L illustrates removing the second hardmask 442(2) and forming the third blocking layer 432(3) over the thirdbottom interconnect 214(3), the second top electrode film 433(2), andthe first top electrode film 433(1) in the Y-axis direction. In thisexample, the third blocking layer 432(3) is formed over the first topelectrode film 433(1) and the second top electrode film 433(2) toprotect portions of the first and second MTJ stack films 436(1), 436(2)below each of the first and second top electrode films 433(1), 433(2)from etching, as will be discussed in greater detail below. The thirdblocking layer 432(3) is also formed over the second blocking layer432(2) to form the third blocking layer 432(3) without potentiallydamaging the bottom electrode film 434, as similarly discussed above.FIG. 4M illustrates removing a portion of the third blocking layer432(3) to expose the third bottom interconnect 214(3) of the third MRAMarray 208(3). In this example, a third photoresist mask 438(3) is usedto expose the portion of the third blocking layer 432(3) to be removed.In this manner, the third blocking layer 432(3) can cover the first topelectrode film 433(1) and the second top electrode film 433(2) so that athird MTJ stack film 436(3), introduced in a later step, can bedeposited above the exposed third bottom interconnect 214(3) withoutbeing deposited directly above the first and second top electrode films433(1), 433(2). The third photoresist can be deposited using a processsuch as spin coating, as a non-limiting example.

FIG. 4N illustrates a cross-sectional view of a fourteenth fabricationstage 400(14) of depositing the third MTJ stack film 436(3) in theY-axis direction over the third bottom interconnect 214(3) of the thirdMRAM array 208(3). Further, FIG. 4N illustrates depositing a third topelectrode film 433(3) over the third MTJ stack film 436(3) in the Y-axisdirection. As shown in FIG. 4N, depositing the third MTJ stack film436(3) includes depositing a third free film 439(3), a third tunnelbarrier film 440(3), and a third pinned film 441(3). In this example,the third MTJ stack film 436(3) is deposited conformally over the bottomelectrode film 434 in the third MRAM array 208(3) and over the thirdblocking layer 432(3) in the first MRAM array 208(1) and the second MRAMarray 208(2). Similarly, the third top electrode film 433(3) isdeposited conformally over the third MTJ stack film 436(3). The thirdMTJ stack film 436(3) can be formed by a process such as PVD and cancomprise materials such as Ta/TaN, Co, Pt, PtMn, CoFe, CoFeB, MgO, Ru,HfIr, Ta, TbCoFe, and/or TbWFe, as non-limiting examples. Additionally,the third top electrode film 433(3) can be formed by a process such asPVD and can comprise materials such as Ta, TaN, Ru, Ti, TiN, and/or W,as non-limiting examples.

FIG. 4O illustrates a cross-sectional view of a fifteenth fabricationstage 400(15) of depositing a third mask, which is third hard mask442(3) over a portion of the third top electrode film 433(3) in theY-axis direction. As shown in FIG. 4O, the third hard mask 442(3) isdeposited over the portion of the third top electrode film 433(3) overthe third MTJ stack film 436(3) over the third bottom interconnect214(3). In this manner, the third hard mask 442(3) covers the portion ofthe third top electrode film 433(3) above the third bottom interconnect214(3), protecting the portion of the third top electrode film 433(3)and a portion of the third MTJ stack film 436(3) thereunder frometching, as will be discussed in further detail below. The third hardmask 442(3) can be deposited using processes such as CVD or PVD and cancomprise materials such as SiO2, SiNx, and/or SiCN, as non-limitingexamples.

FIG. 4P illustrates a cross-sectional view of a sixteenth fabricationstage 400(16) of removing a portion of the third top electrode film433(3) and a portion of the third MTJ stack film 436(3) not under thethird hard mask 442(3). In this regard, a portion of the third topelectrode film 433(3) and a portion of the third MTJ stack film 436(3)not covered by the third hard mask 442(3) are removed. The thirdblocking layer 432(3) covers and protects the first top electrode film433(1) and the second top electrode film 433(2) from being removed. Inthis manner, the integrity of the first and second top electrode films433(1), 433(2), as well as the first and second MTJ stack films 436(1),436(2) thereunder, can be maintained so that each MTJ stack film 436(1),436(2) and each top electrode film 433(1), 433(2) can later be formedinto the first MTJ 202(1) and the second MTJ 202(2). In this example,removal may include processes such as etching, ion miller physicaletching, plasma chemical etching, and/or cleaning processes, asnon-limiting examples. Etchants may include CF4, C12SF6 C4F8, and/orCHF3, as non-limiting examples.

FIG. 4Q illustrates a cross-sectional view of a seventeenth fabricationstage 400(17) of removing the third hard mask 442(3) and the thirdblocking layer 432(3). In this regard, the third hard mask 442(3) may beremoved through processes including wet etching, plasma chemicaletching, and/or cleaning processes, as non-limiting examples. The thirdblocking layer 432(3) may be removed through processes including wetetching, plasma chemical etching, and/or cleaning processes, asnon-limiting examples. If the third hard mask 442(3) is made of the samematerial as the third blocking layer 432(3), the third hard mask 442(3)can be removed in a manner similar to and/or simultaneous with theremoval of the third blocking layer 432(3). Where possible, this removalprocess can also be applied to removing any of the first, second, andthird hard masks 442(1)-442(3) and the first, second, and third blockinglayers 432(1)-432(3). In this example, removal may include processessuch as etching, ion miller physical etching, plasma chemical etching,and/or cleaning processes, as non-limiting examples. Etchants mayinclude CF4, C12SF6 C4F8, and/or CHF3, as non-limiting examples.

FIGS. 4R-4S illustrate cross-sectional views of additional fabricationstages 400(18), 400(19) of forming each MTJ stack 204(1)-204(3) suchthat each MTJ stack 204(1)-204(3) has an energy barrierE_(b(1))-E_(b(3)) different from the energy barrier E_(b(1))-E_(b(3)) ofanother MTJ stack 204(1)-204(3). In this regard, forming each MTJ stack204(1)-204(3) includes depositing a fourth photoresist mask 438(4) inthe Y-axis direction to selectively expose portions of each topelectrode film 433(1)-433(3). By selectively exposing a portion of eachtop electrode film 433(1)-433(3), portions of each top electrode film433(1)-433(3) and each MTJ stack film 436(1)-436(3) of each MRAM array208(1)-208(3) can be selectively removed. Similarly, portions of thebottom electrode film 434 can be selectively removed to form bottomelectrode layers 210(1)-210(3). In this manner, the widths W₁-W₃ of eachMTJ stack film 436(1)-436(3) can be controlled to form each MTJ stack204(1)-204(3) with an energy barrier E_(b(1))-E_(b(3)) different fromthe energy barrier E_(b(1))-E_(b(3)) of another MTJ stack 204(1)-204(3).FIG. 4S illustrates removing the fourth photoresist mask 438(4) to formfirst, second, and third MTJs 202(1)-202(3) having first, second, andthird MTJ stacks 204(1)-204(3) including varying materials and/or widthsto vary energy barriers E_(b(1))-E_(b(3)) of the MTJ stacks204(1)-204(3), as provided in FIG. 2B. By forming the first, second, andthird MTJs 202(1)-202(3) in this manner, the MTJs 202(1)-202(3) andaccess transistors 228(1)-228(3) provided in FIG. 2B can be implementedin various MRAM bit cell devices in different MRAM arrays 208(1)-208(3)to provide different types of memory in the same semiconductor die 200while still achieving distinct performance specifications.

FIGS. 5A-5R illustrate an alternative method of fabricating the MTJs202(1)-202(3) having MTJ stacks 204(1)-204(3) including varyingmaterials and/or widths to vary energy barriers E_(b(1))-E_(b(3)) of theMTJ stacks 204(1)-204(3), as provided in FIG. 2B. The fabrication methodillustrated in FIGS. 5A-5R is different from the fabrication methodillustrated in FIGS. 4A-4S in that a bottom electrode film 534(1)-534(3)is included in each MTJ stack film 536(1)-536(3) in FIGS. 5A-5R. Incontrast, the bottom electrode film 434 in FIGS. 4A-4S is included inthe interconnect layer 216 and selectively removed after depositing eachMTJ stack film 436(1)-436(3) to form each bottom electrode layer210(1)-210(3). Thus, the alternative method of fabricating the MTJs202(1)-202(3) illustrated in FIGS. 5A-5R is distinguished from thefabrication method illustrated in FIGS. 4A-4S by the manner in which thebottom electrode film 534(1)-534(3) is deposited.

FIGS. 5A-5B illustrate cross-sectional views of first and secondfabrication stages 500(1), 500(2) of fabricating a first blocking layer532(1) (shown in FIG. 5B) in the Y-axis direction over the second bottominterconnect 214(2) of the second MRAM array 208(2). FIGS. 5A and 5Billustrate forming the first blocking layer 532(1) over the secondbottom interconnect 214(2) of the second MRAM array 208(2) and the thirdbottom interconnect 214(3) of the third MRAM array 208(3). In thisexample, a first photoresist mask 538(1) is used to form the firstblocking layer 532(1). In this manner, the first blocking layer 532(1)is formed over the second bottom interconnect 214(2) of the second MRAMarray 208(2) and the third bottom interconnect 214(3) of the third MRAMarray 208(3).

FIG. 5C illustrates a cross-sectional view of a third fabrication stage500(3) of depositing the first MTJ stack film 536(1) in the Y-axisdirection over the first bottom interconnect 214(1) of the first MRAMarray 208(1) and at least a portion of the first blocking layer 532(1).The third fabrication stage 500(3) in FIG. 5C further illustratesdepositing a first top electrode film 533(1) over the first MTJ stackfilm 536(1). As shown in FIG. 5C, depositing the first MTJ stack film536(1) includes depositing a first bottom electrode film 534(1), a firstfree film 539(1), a first tunnel barrier film 540(1), and a first pinnedfilm 541(1). In this example, the first MTJ stack film 536(1) isdeposited conformally over the interconnect layer 216 in the first MRAMarray 208(1) and over the first blocking layer 532(1) in the second MRAMarray 208(2) and the third MRAM array 208(3). The first MTJ stack film536(1) can be formed by a process such as PVD and can comprise materialssuch as Ta/TaN, Co, Pt, PtMn, CoFe, CoFeB, MgO, Ru, and/or HfIr, Ta,TbCoFe, TbWFe, as non-limiting examples. Additionally, the first topelectrode film 533(1) can be formed by a process such as PVD, and cancomprise materials such as Ta, TaN, Ru, Ti, TiN, and/or W, asnon-limiting examples. The first bottom electrode film 534(1) can beformed by a process such as PVD, and can comprise materials such as Ta,TaN, Ti/TiN, W, Ru, PtMn, and/or Co/Pt, as non-limiting examples.

FIG. 5D illustrates a cross-sectional view of a fourth fabrication stage500(4) of depositing a first mask, which is first hard mask 542(1) inthis example, in the Y-axis direction over a portion of the first topelectrode film 533(1). As shown in FIG. 5D, the first hard mask 542(1)is deposited over the portion of the first top electrode film 533(1)over the first MTJ stack film 536(1) over the first bottom interconnect214(1). In this manner, the first hard mask 542(1) covers the portion ofthe first top electrode film 533(1) above the first bottom interconnect214(1), protecting a portion of the first top electrode film 533(1) anda portion of the first MTJ stack film 536(1) thereunder from etching, aswill be discussed in further detail below. The first hard mask 542(1)can be deposited using processes such as CVD and PVD, and can comprisematerials such as SiO2, SiNx, SiCN, SiON, and/or SiCON, as non-limitingexamples.

FIG. 5E illustrates a cross-sectional view of a fifth fabrication stage500(5) of removing a portion of the first top electrode film 533(1) anda portion of the first MTJ stack film 536(1) not under the first hardmask 542(1). In this regard, a portion of the first top electrode film533(1) and a portion of the first MTJ stack film 536(1) not covered bythe first hard mask 542(1) are removed. The first blocking layer 532(1)is not removed as it is used in this example to cover and protect thesecond bottom interconnect 214(2) and the third bottom interconnect214(3). In this example, removal may include processes such as etching,ion miller physical etching, plasma chemical etching, and/or cleaningprocesses, as non-limiting examples. Etchants may include CF4, C12SF6C4F8, and/or CHF3, as non-limiting examples.

FIGS. 5F-5G illustrate cross-sectional views of sixth and seventhfabrication stages 500(6), 500(7) of removing at least a portion of thefirst blocking layer 532(1) over the second bottom interconnect 214(2)of the second MRAM array 208(2). In this regard, FIG. 5F illustratesremoving the first hard mask 542(1) and forming a second blocking layer532(2) over the second bottom interconnect 214(2), the third bottominterconnect 214(3), and the first top electrode film 533(1). In thisexample, the second blocking layer 532(2) is formed in the Y-axisdirection over the first blocking layer 532(1) and the first topelectrode film 533(1) to protect a portion of the first top electrodefilm 533(1) and a portion of the first MTJ stack film 536(1) thereunderfrom etching, as will be discussed in further detail below. FIG. 5Gillustrates removing a portion of the first blocking layer 532(1) and aportion of the second blocking layer 532(2) to expose the second bottominterconnect 214(2) of the second MRAM array 208(2). In this example, asecond photoresist mask 538(2) is used to expose the portion of thefirst blocking layer 532(1) to be removed. In this manner, a second MTJstack film 536(2) shown in a later step may be deposited above theexposed second bottom interconnect 214(2). In alternative methods,instead of forming the second blocking layer 532(2) over the firstblocking layer 532(1), the first blocking layer 532(1) can be removedand the second blocking layer 532(2) can be deposited thereafter.However, this alternative method may not be desirable because removingthe first blocking layer 532(1) may damage the interconnect layer 216through mechanisms such as oxidative damage. The second photoresist mask538(2) can be deposited using a process such as spin coating, as anon-limiting example.

FIG. 5H illustrates a cross-sectional view of an eighth fabricationstage 500(8) of depositing a second MTJ stack film 536(2) in the Y-axisdirection over the second bottom interconnect 214(2) of the second MRAMarray 208(2) and at least a portion of the second blocking layer 532(2).Further, FIG. 5H illustrates depositing a second top electrode film533(2) over the second MTJ stack film 536(2). As shown in FIG. 5H,depositing the second MTJ stack film 536(2) includes depositing a secondbottom electrode film 534(2), a second free film 539(2), a second tunnelbarrier film 540(2), and a second pinned film 541(2). In this example,the second MTJ stack film 536(2) is deposited conformally over theinterconnect layer 216 in the second MRAM array 208(2) and over thesecond blocking layer 532(2) in the first MRAM array 208(1) and thethird MRAM array 208(3). The second MTJ stack film 536(2) can be formedby a process such as PVD and can comprise materials such as Ta/TaN, Co,Pt, PtMn, CoFe, CoFeB, MgO, Ru, HfIr, and/or Ta, as non-limitingexamples. The second top electrode film 533(2) can be formed by aprocess such as PVD and can comprise materials such as Ta, TaN, Ru, Ti,TiN, and/or W, as non-limiting examples. The second bottom electrodefilm 534(2) can be formed by a process such as PVD and can comprisematerials such as Ta, TaN, Ti/TiN, W, Ru, PtMn, and/or Co/Pt, asnon-limiting examples.

FIG. 5I illustrates a cross-sectional view of a ninth fabrication stage500(9) of depositing the second mask, which is second hard mask 542(2)in this example, in the Y-axis direction over a portion of the secondtop electrode film 533(2). As shown in FIG. 5I, the second hard mask542(2) is deposited over the portion of the second top electrode film533(2) over the second MTJ stack film 536(2) over the second bottominterconnect 214(2). In this manner, the second hard mask 542(2) coversthe portion of the second top electrode film 533(2) above the secondbottom interconnect 214(2), protecting the portion of the second topelectrode film 533(2) and a portion of the second MTJ stack film 536(2)thereunder from etching, as will be discussed in further detail below.The second hard mask 542(2) can be deposited using processes such as CVDand PVD, and can comprise materials such as SiO2, SiNx, SiON, SiCON,and/or SiCN, as non-limiting examples.

FIG. 5J illustrates a cross-sectional view of a tenth fabrication stage500(10) of removing a portion of the second top electrode film 533(2)and a portion of the second MTJ stack film 536(2) not under the secondhard mask 542(2). In this regard, a portion of the second top electrodefilm 533(2) and a portion of the second MTJ stack film 536(2) notcovered by the second hard mask 542(2) are removed. The second blockinglayer 532(2) is not removed as it is used in this example to cover andprotect the first top electrode film 533(1), the first MTJ stack film536(1), and the third bottom interconnect 214(3). In this example,removal may include processes such as etching, ion miller physicaletching, plasma chemical etching, and/or cleaning processes, asnon-limiting examples. Etchants may include CF4, C12SF6 C4F8, and/orCHF3, as non-limiting examples.

FIGS. 5K-5L illustrate cross-sectional views of eleventh and twelfthfabrication stages 500(11), 500(12) of depositing a third blocking layer532(3) in the Y-axis direction and removing at least a portion of thethird blocking layer 532(3) over the third bottom interconnect 214(3) ofthe third MRAM array 208(3). In this regard, FIG. 5K illustratesremoving the second hard mask 542(2) and forming the third blockinglayer 532(3) over the third bottom interconnect 214(3), the second topelectrode film 533(2), and the first top electrode film 533(1). In thisexample, the third blocking layer 532(3) is formed over the first topelectrode film 533(1) and the second top electrode film 533(2) toprotect portions of the first and second MTJ stack films 536(1), 536(2)below each of the first and second top electrode films 533(1), 533(2)from etching, as will be discussed in greater detail below. The thirdblocking layer 532(3) is also formed over the second blocking layer532(2) to form the third blocking layer 532(3) without potentiallydamaging the interconnect layer 216, as similarly discussed above. FIG.5L illustrates removing a portion of the third blocking layer 532(3) toexpose the third bottom interconnect 214(3) of the third MRAM array208(3). In this example, a third photoresist mask 538(3) is used toexpose the portion of the third blocking layer 532(3) to be removed. Inthis manner, the third blocking layer 532(3) can cover the first topelectrode film 533(1) and the second top electrode film 533(2) so that athird MTJ stack film 536(3) can be deposited above the exposed thirdbottom interconnect 214(3) without being deposited directly above thefirst and second top electrode films 533(1), 533(2). The thirdphotoresist mask 538(3) can be deposited using processes such as spincoating and baking at high temperatures, such as temperatures betweenapproximately 100-250° C., as non-limiting examples.

FIG. 5M illustrates a cross-sectional view of a thirteenth fabricationstage 500(13) of depositing the third MTJ stack film 536(3) in theY-axis direction over the third bottom interconnect 214(3) of the thirdMRAM array 208(3). Further, FIG. 5M illustrates depositing a third topelectrode film 533(3) over the third MTJ stack film 536(3). As shown inFIG. 5M, depositing the third MTJ stack film 536(3) includes depositinga third bottom electrode film 534(3), a third free film 539(3), a thirdtunnel barrier film 540(3), and a third pinned film 541(3). In thisexample, the third MTJ stack film 536(3) is deposited conformally overthe interconnect layer 216 in the third MRAM array 208(3) and over thethird blocking layer 532(3) in the first MRAM array 208(1) and thesecond MRAM array 208(2). Similarly, the third top electrode film 533(3)is deposited conformally over the third MTJ stack film 536(3). The thirdMTJ stack film 536(3) can be formed by a process such as PVD, and cancomprise materials such as Ta/TaN, Co, Pt, PtMn, CoFe, CoFeB, MgO, Ru,Ta, and/or HfIr, as non-limiting examples. The third top electrode film533(3) can be formed by a process such as PVD and can comprise materialssuch as Ta, TaN, Ru, Ti, TiN, and/or W, as non-limiting examples. Thethird bottom electrode film 534(3) can be formed by a process such asPVD and can comprise materials such as Ta, TaN, Ti/TiN, W, Ru, PtMn,and/or Co/Pt, as non-limiting examples.

FIG. 5N illustrates a cross-sectional view of a fourteenth fabricationstage 500(14) of depositing a third mask, which is third hard mask542(3) in this example, in the Y-axis direction over a portion of thethird top electrode film 533(3). As shown in FIG. 5N, the third hardmask 542(3) is deposited over the portion of the third top electrodefilm 533(3) over the third MTJ stack film 536(3) over the third bottominterconnect 214(3). In this manner, the third hard mask 542(3) coversthe portion of the third top electrode film 533(3) above the thirdbottom interconnect 214(3), protecting the portion of the third topelectrode film 533(3) and a portion of the third MTJ stack film 536(3)thereunder from etching, as will be discussed in further detail below.The third hard mask 542(3) can be deposited using processes such as CVDor PVD and can comprise materials such as SiO2, SiNx, SiON, SiCON,and/or SiCN, as non-limiting examples.

FIG. 5O illustrates a cross-sectional view of a fifteenth fabricationstage 500(15) of removing a portion of the third top electrode film533(3) and a portion of the third MTJ stack film 536(3) not under thethird hard mask 542(3). In this regard, a portion of the third topelectrode film 533(3) and a portion of the third MTJ stack film 536(3)not covered by the third hard mask 542(3) are removed. The thirdblocking layer 532(3) covers and protects the first top electrode film533(1) and the second top electrode film 533(2) from being removed. Inthis manner, the integrity of the first and second top electrode films533(1), 533(2), as well as the first and second MTJ stack films 536(1),536(2) thereunder, can be maintained so that each MTJ stack film 536(1),536(2) and each top electrode film 533(1), 533(2) can later be formedinto the first MTJ 202(1) and the second MTJ 202(2). In this example,removal may include processes such as etching, ion miller physicaletching, plasma chemical etching, and/or cleaning processes, asnon-limiting examples. Etchants may include CF4, C12SF6 C4F8, and/orCHF3, as non-limiting examples.

FIG. 5P illustrates a cross-sectional view of a sixteenth fabricationstage 500(16) of removing the third hard mask 542(3) and the thirdblocking layer 532(3). In this regard, the third hard mask 542(3) may beremoved through processes including wet etching, dry etching, and/orcleaning processes, as non-limiting examples. The third blocking layer532(3) may be removed through processes including wet etching, dryetching, and/or cleaning processes, as non-limiting examples. If thethird hard mask 542(3) is made of the same material as the thirdblocking layer 532(3), the third hard mask 542(3) can be removed in amanner similar to and/or simultaneous with the removal of the thirdblocking layer 532(3). Where possible, this removal process can also beapplied to removing any of the first, second, and third hard masks542(1)-542(3) and the first, second, and third blocking layers532(1)-532(3). In this example, removal may include processes such asetching, ion miller physical etching, plasma chemical etching, and/orcleaning processes, as non-limiting examples. Etchants may include CF4,C12SF6 C4F8, and/or CHF3, as non-limiting examples.

FIGS. 5Q-5R illustrate cross-sectional views of seventeenth andeighteenth fabrication stages 500(17), 500(18) of forming each MTJ stack204(1)-204(3) such that each MTJ stack 204(1)-204(3) has an energybarrier E_(b(1))-E_(b(3)) different from the energy barrierE_(b(1))-E_(b(3)) of another MTJ stack 204(1)-204(3). In this regard,forming each MTJ stack 204(1)-204(3) includes depositing a fourthphotoresist mask 538(4) to selectively expose portions of each topelectrode film 533(1)-533(3) shown in FIG. 5P. By selectively exposingportion of each top electrode film 533(1)-533(3), portions of each topelectrode film 533(1)-533(3) and each MTJ stack film 536(1)-536(3) ofeach MRAM array 208(1)-208(3) can be selectively removed. In thismanner, the widths W₁-W₃ of each MTJ stack film 536(1)-536(3) can becontrolled so as to form each MTJ stack 204(1)-204(3) with an energybarrier E_(b(1))-E_(b(3)) different from the energy barrierE_(b(1))-E_(b(3)) of another MTJ stack 204(1)-204(3). FIG. 5Rillustrates removing the fourth photoresist mask 538(4) to form first,second, and third MTJs 202(1)-202(3) having first, second, and third MTJstacks 204(1)-204(3) including varying materials and/or widths to varyenergy barriers E_(b(1))-E_(b(3)) of the MTJ stacks 204(1)-204(3), asprovided in FIG. 2B. By forming the first, second, and third MTJs202(1)-202(3) in this manner, the MTJs 202(1)-202(3) and accesstransistors 228(1)-228(3) provided in FIG. 2B can be implemented invarious MRAM bit cell devices in different MRAM arrays 208(1)-208(3) toprovide different types of memory in the same semiconductor die 200while still achieving distinct performance specifications.

FIGS. 6A-6C, 7A-7D, 8A-8C, and 9A-9D illustrate methods of forming MRAMbit cells having varying structures from the MTJs 202(1)-202(3) providedin FIGS. 2A and 2B. In this manner, the MTJs 202(1)-202(3) havingvarying energy barriers provided in FIG. 2B, and formed in exemplaryfabrication processes such as FIGS. 4A-4S and 5A-5R, can be implementedin MRAM bit cells formed and provided in FIGS. 6A-6C, 7A-7D, 8A-8C, and9A-9D in different MRAM arrays 208(1)-208(3) in the semiconductor die200. By providing MTJs 202(1)-202(3) having varying energy barriers inMRAM bit cells in different MRAM arrays 208(1)-208(3), different typesof memory can be provided in the semiconductor die 200 while stillachieving distinct performance specifications, such as access times,data retention rates, bit cell endurances, array densities, and/or powerconsumption rates, as examples.

In this regard, FIGS. 6A-6C illustrate cross-sectional views at variousstages of forming MRAM bit cells 201(1)-201(3) (shown in FIG. 6C) havinga spacer film 642 over the interconnect layer 216 and a top metal line650(1)-650(3) as a top interconnect 644(1)-644(3) in different MRAMarrays 208(1)-208(3) from the MTJ stacks 204(1)-204(3) having varyingenergy barriers E_(b(1))-E_(b(3)), as provided in FIG. 2B. In thisregard, FIG. 6A illustrates a cross-sectional view of a firstfabrication stage 600(1) of forming the spacer film 642 adjacent to eachMTJ stack 204(1)-204(3). FIG. 6A further illustrates depositing adielectric layer 652 adjacent to the spacer film 642 and over each MTJstack 204(1)-204(3) in the Y-axis direction. As shown in FIG. 6A, thespacer film 642 is formed over each of the MTJs 202(1)-202(3) and overthe interconnect layer 216 in a conformal manner The dielectric layer652 is deposited over the spacer film 642. The spacer film 642 can bedeposited using processes such as CVD or PVD and can comprise materialssuch as SiO2, SiON, silicon carbide (SiC), SiCN, SiCON, aluminum oxide(AlOx), and/or SiNx, as non-limiting examples. The dielectric layer 652can be deposited using processes such as CVD, PVD, spin coating, and/orultraviolet (UV) curing and can comprise a material such as SiO2, as anon-limiting example. The dielectric layer 652 can be further processedby processes such as CMP, and cleaning processes, as non-limitingexamples.

FIG. 6B illustrates a cross-sectional view of a second fabrication stage600(2) of removing a portion of the dielectric layer 652 over each MTJstack 204(1)-204(3) to expose a top surface 654(1)-654(3) of each topelectrode layer 209(1)-209(3). In this regard, a first top photoresistmask 656 is used to expose the portion of the dielectric layer 652 to beremoved. The selected portions of the dielectric layer 652 above the topsurface 654(1)-654(3) of each top electrode layer 209(1)-209(3) are thenremoved. In this manner, the top metal lines 650(1)-650(3) can be formedtherein. The first top photoresist mask 656 can be used in processessuch as photolithography and etching and can comprise materials such asphotoresist materials, as non-limiting examples. Removing the dielectriclayer 652 can comprise processes such as dry etching, and cleaningprocesses, as non-limiting examples.

FIG. 6C illustrates a cross-sectional view of a third fabrication stage600(3) of fabricating each top interconnect 644(1)-644(3) in the Y-axisdirection over the top surface 654(1)-654(3) of each respective topelectrode layer 209(1)-209(3). In this regard, each top interconnect644(1)-644(3) includes a top metal line 650(1)-650(3), which isdeposited over the top surface 654(1)-654(3) of each respective topelectrode layer 209(1)-209(3). A top diffusion barrier 658 is formedabove the top interconnect 644(1)-644(3). Each top interconnect644(1)-644(3) can be deposited in processes such as PVD, electricalplating, CMP, and/or cleaning processes, and can comprise materials suchas Ta/TaN, and Cu, as non-limiting examples. The top diffusion barrier658 can be deposited using processes such as CVD or PVD and can comprisematerials such as SiCN, and/or SiNx, as non-limiting examples. In thismanner, the MTJs 202(1)-202(3) having varying energy barriers providedin FIG. 2B, and formed in exemplary fabrication processes such as FIGS.4A-4S and 5A-5R, can be implemented in MRAM bit cells 201(1)-201(3) indifferent MRAM arrays 208(1)-208(3) in the semiconductor die 200.

In this regard, FIGS. 7A-7D illustrate cross-sectional views at variousstages of forming MRAM bit cells 201(1)-201(3) having a spacer film 746over the interconnect layer 216 and a top via 748V(1)-748V(3) and a topmetal line 750M(1)-750M(3) as a top interconnect 744(1)-744(3) indifferent MRAM arrays 208(1)-208(3) from the MTJ stacks 204(1)-204(3)having varying energy barriers E_(b(1))-E_(b(3)), as provided in FIG.2B. In this regard, FIG. 7A illustrates a cross-sectional view of afirst fabrication stage 700(1) of forming the spacer film 746 adjacentto each MTJ stack 204(1)-204(3). FIG. 7A further illustrates depositinga dielectric layer 752 adjacent to the spacer film 746 and over each MTJstack 204(1)-204(3). As shown in FIG. 7A, the spacer film 746 is formedover each of the MTJs 202(1)-202(3) and over the interconnect layer 216in a conformal manner The dielectric layer 752 is deposited over thespacer film 746. The spacer film 746 can be deposited using processessuch as CVD or PVD and can comprise materials such as SiO2, SiON, SiC,SiCN, SiCON, AlOx, and/or SiNx, as non-limiting examples. The dielectriclayer 752 can be deposited using processes such as CVD, PVD, spincoating, and/or UV curing, and can comprise a material such as SiO2, asnon-limiting examples. The dielectric layer 752 can be further processedby processes such as CMP and/or cleaning processes, as non-limitingexamples.

FIG. 7B illustrates a cross-sectional view of a second fabrication stage700(2) of removing a portion of the dielectric layer 752 over each MTJstack 204(1)-204(3) to expose a top surface 754(1)-754(3) of each topelectrode layer 209(1)-209(3). In this regard, a first top photoresistmask 756(1) is used to expose the portion of the dielectric layer 752 tobe removed. The selected portions of the dielectric layer 752 above thetop surface 754(1)-754(3) of each top electrode layer 209(1)-209(3) arethen removed. The first top photoresist mask 756(1) can be used inprocesses such as spin coating, and photolithography, and can comprisematerials such as photoresist materials, as non-limiting examples.Removing the dielectric layer 752 can comprise processes such as dryetching, and cleaning processes, as non-limiting examples.

FIG. 7C illustrates a cross-sectional view of a third fabrication stage700(3) of removing additional portions of the dielectric layer 752 overeach MTJ stack 204(1)-204(3) to allow each top via 748V(1)-748V(3) andeach top metal line 750M(1)-750M(3), shown in a later step, to be formedas each top interconnect 744(1)-744(3). In this regard, FIG. 7Cillustrates using a second top photoresist mask 756(2) to expose theadditional portions of the dielectric layer 752 to be removed. Theselected additional portions of the dielectric layer 752 are thenremoved. The second top photoresist mask 756(2) can be used in processessuch as spin coating, and photolithography and can comprise materialssuch as photoresist materials as non-limiting examples. Removing thedielectric layer 752 can comprise processes such as dry etching, andcleaning processes, as non-limiting examples.

FIG. 7D illustrates a cross-sectional view of a fourth fabrication stage700(4) of forming each top interconnect 744(1)-744(3) in the Y-axisdirection over the top surface 754(1)-754(3) of each respective topelectrode layer 209(1)-209(3). In this regard, each top interconnect744(1)-744(3) includes a top via 748V(1)-748V(3) and a top metal line750M(1)-750M(3), which are deposited over the top surface 754(1)-754(3)of each respective top electrode layer 209(1)-209(3). A top diffusionbarrier 758 is formed above the top interconnect 744(1)-744(3). Each topinterconnect 744(1)-744(3) can be deposited in processes such as PVD,electrical plating, CMP, and/or cleaning processes, and can comprisematerials such as Ta/TaN, and/or Cu, as non-limiting examples. The topdiffusion barrier 758 can be deposited in processes such as CVD and PVD,and can comprise materials such as SiCN, and/or SiNx, as non-limitingexamples. In this manner, the MTJs 202(1)-202(3) having varying energybarriers provided in FIG. 2B, and formed in exemplary fabricationprocesses such as FIGS. 4A-4S and 5A-5R, can be implemented in MRAM bitcells 201(1)-201(3) in different MRAM arrays 208(1)-208(3) in thesemiconductor die 200.

In this regard, FIGS. 8A-8C illustrate cross-sectional views at variousstages of forming MRAM bit cells 201(1)-201(3) having a spacer film 846adjacent to each MTJ stack 204(1)-204(3) and a top via 850(1)-850(3) asa top interconnect 844(1)-844(3) in different MRAM arrays 208(1)-208(3)from the MTJ stacks 204(1)-204(3) having varying energy barriersE_(b(1))-E_(b(3)), as provided in FIG. 2B. In this regard, FIG. 8Aillustrates a cross-sectional view of a first fabrication stage 800(1)of forming the spacer film 846 adjacent to each MTJ stack 204(1)-204(3)to expose a top surface 860 of the interconnect layer 216 of thesemiconductor die 200 and a top surface 854(1)-854(3) of each topelectrode layer 209(1)-209(3) from the spacer film 846. FIG. 8A furtherillustrates depositing a dielectric layer 852 adjacent to the spacerfilm 846, over each MTJ stack 204(1)-204(3), and over the exposed topsurface 860 of the interconnect layer 216. As shown in FIG. 8A, thespacer film 846 is formed laterally adjacent to each of the MTJs202(1)-202(3). The dielectric layer 852 is deposited over the spacerfilm 846 and the top surface 860 of the interconnect layer 216. Thespacer film 846 can be deposited using processes such as CVD, PVD,and/or dry etch back, and can comprise materials such as SiO2, SiON,SiC, SiCN, SiCON, AlOx, and/or SiNx, as non-limiting examples. Thedielectric layer 852 can be deposited using processes such as CVD and/orPVD and can comprise a material such as SiO2. The dielectric layer 852can be further processed by processes such as CMP and/or cleaningprocesses, as non-limiting examples.

FIG. 8B illustrates a cross-sectional view of a second fabrication stage800(2) of removing a portion of the dielectric layer 852 over each MTJstack 204(1)-204(3) to expose a top surface 854(1)-854(3) of each topelectrode layer 209(1)-209(3). In this regard, a first top photoresistmask 856(1) is used to expose the portion of the dielectric layer 852 tobe removed. The selected portions of the dielectric layer 852 above thetop surface 854(1)-854(3) of each top electrode layer 209(1)-209(3) arethen removed. In this manner, the top metal lines 850(1)-850(3) can beformed therein in a later step. The first top photoresist mask 856(1)can be used in processes such as spin coating, photolithography, andbaking, and can comprise materials such as photoresist materials asnon-limiting examples. Removing the dielectric layer 852 can compriseprocesses such as dry etching, and cleaning processes, as non-limitingexamples.

FIG. 8C illustrates a cross-sectional view of a third fabrication stage800(3) of fabricating each top interconnect 844(1)-844(3) in the Y-axisdirection over the top surface 854(1)-854(3) of each respective topelectrode layer 209(1)-209(3). In this regard, each top interconnect844(1)-844(3) includes a top metal line 850(1)-850(3), which isdeposited over the top surface 854(1)-854(3) of each respective topelectrode layer 209(1)-209(3). A top diffusion barrier 858 is formedabove the top interconnect 844(1)-844(3). Each top interconnect844(1)-844(3) can be deposited in processes such as PVD, electricalplating, CMP, and/or cleaning processes, and can comprise materials suchas Ta/TaN, and/or Cu, as non-limiting examples. The top diffusionbarrier 858 can be deposited in processes such as CVD or PVD and cancomprise materials such as SiCN, and/or SiNx, as non-limiting examples.In this manner, the MTJs 202(1)-202(3) having varying energy barriersE_(b(1))-E_(b(3)) provided in FIG. 2B, and formed in exemplaryfabrication processes such as FIGS. 4A-4S and 5A-5R, can be implementedin MRAM bit cells 201(1)-201(3) in different MRAM arrays 208(1)-208(3)in the semiconductor die 200.

In this regard, FIGS. 9A-9C illustrate cross-sectional views at variousstages of fabricating MRAM bit cells 201(1)-201(3) having a spacer film946 adjacent to each MTJ stack 204(1)-204(3) and a top via948V(1)-948V(3) and a top metal line 950M(1)-950M(3) as a topinterconnect 944(1)-944(3) in different MRAM arrays 208(1)-208(3) fromthe MTJ stacks 204(1)-204(3) having varying energy barriersE_(b(1))-E_(b(3)), as provided in FIG. 2B. In this regard, FIG. 9Aillustrates a cross-sectional view of a first fabrication stage 900(1)of forming the spacer film 946 adjacent to each MTJ stack 204(1)-204(3)to expose a top surface 960 of the interconnect layer 216 of thesemiconductor die 200 and a top surface 954(1)-954(3) of each topelectrode layer 209(1)-209(3) from the spacer film 946. FIG. 9A furtherillustrates depositing a dielectric layer 952 adjacent to the spacerfilm 946, over each MTJ stack 204(1)-204(3), and over the exposed topsurface 960 of the interconnect layer 216. As shown in FIG. 8A, thespacer film 946 is formed laterally adjacent to each of the MTJs202(1)-202(3). The dielectric layer 952 is deposited over the spacerfilm 946 and the top surface 960 of the interconnect layer 216. Thespacer film 946 can be deposited using processes such as CVD, PVD,and/or dry etch back, and can comprise materials such as SiO2, SiON,SiC, SiCN, SiCON, AlOx, and/or SiNx, as non-limiting examples. Thedielectric layer 952 can be deposited using processes such as CVD, PVD,spin coating, and/or UV curing, and can comprise a material such asSiO2, as non-limiting examples. The dielectric layer 952 can be furtherprocessed by processes such as CMP and/or cleaning processes, asnon-limiting examples.

FIG. 9B illustrates a cross-sectional view of a second fabrication stage900(2) of removing a portion of the dielectric layer 952 over each MTJstack 204(1)-204(3) to expose a top surface 954(1)-954(3) of each topelectrode layer 209(1)-209(3). In this regard, a first top photoresistmask 956(1) is used to expose the portion of the dielectric layer 952 tobe removed. The selected portions of the dielectric layer 952 above thetop surface 954(1)-954(3) of each top electrode layer 209(1)-209(3) arethen removed. The first top photoresist mask 956(1) can be used inprocesses such as spin coating, photolithography, baking, and/orcleaning processes, and can comprise materials such as photoresistmaterials, as non-limiting examples. Removing the dielectric layer 952can comprise processes such as dry etching, and cleaning processes, asnon-limiting examples.

FIG. 9C illustrates a cross-sectional view of a third fabrication stage900(3) of removing additional portions of the dielectric layer 952 overeach MTJ stack 204(1)-204(3) to allow each top via 948V(1)-948V(3) andeach top metal line 950M(1)-950M(3) to be formed as each topinterconnect 944(1)-944(3). In this regard, FIG. 9C illustrates using asecond top photoresist mask 956(2) to expose the additional portions ofthe dielectric layer 952 to be removed. The selected additional portionsof the dielectric layer 952 are then removed. The second top photoresistmask 956(2) can be used in processes such as spin coating,photolithography, baking, and/or cleaning processes, and can comprisematerials such as photoresist materials, as non-limiting examples.Removing the dielectric layer 952 can comprise processes such as dryetching, and cleaning processes, as non-limiting examples.

FIG. 9D illustrates a cross-sectional view of a fourth fabrication stage900(4) of forming each top interconnect 944(1)-944(3) in the Y-axisdirection over the top surface 954(1)-954(3) of each respective topelectrode layer 209(1)-209(3). In this regard, each top interconnect944(1)-944(3) includes a top via 948V(1)-9V(3) and a top metal line950M(1)-950M(3), which are deposited over the top surface 954(1)-954(3)of each respective top electrode layer 209(1)-209(3). A top diffusionbarrier 958 is formed above the top interconnects 944(1)-944(3). Eachtop interconnect 944(1)-944(3) can be deposited in processes such asPVD, electrical plating, CMP, and/or cleaning processes, and cancomprise materials such as Ta/TaN, and/or Cu, as non-limiting examples.The top diffusion barrier 958 can be deposited in processes such as CVDand/or PVD and can comprise materials such as SiCN, and/or SiNx, asnon-limiting examples. In this manner, the MTJs 202(1)-202(3) havingvarying energy barriers E_(b(1))-E_(b(3)) provided in FIG. 2B, andformed in exemplary fabrication processes such as FIGS. 4A-4S and 5A-5R,can be implemented in MRAM bit cells 201(1)-201(3) in different MRAMarrays 208(1)-208(3) in the semiconductor die 200.

Varying energy barriers of MTJs in different MRAM arrays in asemiconductor die to facilitate use of MRAM for different memoryapplications according to aspects disclosed herein may be provided in orintegrated into any processor-based device. Examples, withoutlimitation, include a set top box, an entertainment unit, a navigationdevice, a communications device, a fixed location data unit, a mobilelocation data unit, a global positioning system (GPS) device, a mobilephone, a cellular phone, a smart phone, a session initiation protocol(SIP) phone, a tablet, a phablet, a server, a computer, a portablecomputer, a mobile computing device, a wearable computing device (e.g.,a smart watch, a health or fitness tracker, eyewear, etc.), a desktopcomputer, a personal digital assistant (PDA), a monitor, a computermonitor, a television, a tuner, a radio, a satellite radio, a musicplayer, a digital music player, a portable music player, a digital videoplayer, a video player, a digital video disc (DVD) player, a portabledigital video player, an automobile, a vehicle component, avionicssystems, a drone, and a multicopter.

In this regard, FIG. 10 illustrates an example of a processor-basedsystem 1000 that can employ MRAM bit cells in MRAM arrays in asemiconductor die having MTJs with varying energy barriers, asillustrated in FIGS. 6A-6C, 7A-7D, 8A-8C, and 9A-9D. In this example,the processor-based system 1000 includes one or more central processingunit(s) (CPU(s)) 1002, each including one or more processors 1004.Although not shown, the CPU(s) 1002 can include at least one CPU core.The CPU(s) 1002 may be a master device. The CPU(s) 1002 may have cachememory 1006 coupled to the processor(s) 1004 for rapid access totemporarily stored data. The CPU(s) 1002 is coupled to a system bus 1008and can intercouple master and slave devices included in theprocessor-based system 1000. As is well known, the CPU(s) 1002communicates with these other devices by exchanging address, control,and data information over the system bus 1008. For example, the CPU(s)1002 can communicate bus transaction requests to a memory controller1010 as an example of a slave device. Although not illustrated in FIG.10, multiple system buses 1008 could be provided, wherein each systembus 1008 constitutes a different fabric.

Other master and slave devices can be connected to the system bus 1008.As illustrated in FIG. 10, these devices can include a memory system1012, one or more input devices 1014, one or more output devices 1016,one or more network interface devices 1018, and one or more displaycontrollers 1020, as examples. The input device(s) 1014 can include anytype of input device, including, but not limited to, input keys,switches, voice processors, etc. The output device(s) 1016 can includeany type of output device, including, but not limited to, audio, video,other visual indicators, etc. The network interface device(s) 1018 canbe any devices configured to allow exchange of data to and from anetwork 1022. The network 1022 can be any type of network, including,but not limited to, a wired or wireless network, a private or publicnetwork, a local area network (LAN), a wireless local area network(WLAN), a wide area network (WAN), a BLUETOOTH™ network, and theInternet. The network interface device(s) 1018 can be configured tosupport any type of communications protocol desired. The memory system1012 can include one or more memory units 1024(0)-1024(M).

The CPU(s) 1002 may also be configured to access the displaycontroller(s) 1020 over the system bus 1008 to control information sentto one or more displays 1026. The display controller(s) 1020 sendsinformation to the display(s) 1026 to be displayed via one or more videoprocessors 1028, which process the information to be displayed into aformat suitable for the display(s) 1026. The display(s) 1026 can includeany type of display, including, but not limited to, a cathode ray tube(CRT), a liquid crystal display (LCD), a plasma display, a lightemitting diode (LED) display, etc.

In another example, a semiconductor die including a first means forstoring data and a second means for storing data can be provided. Thefirst means for storing data comprises a first means for storing a fixedmagnetic moment having a first fixed magnetic moment, and a first meansfor storing a programmable magnetic moment having a first programmablemagnetic moment. The first means for storing data also comprises a firstmeans for transferring spin polarization of electrons disposed betweenthe first means for storing the fixed magnetic moment and the firstmeans for storing the programmable magnetic moment. The first means forstoring data has a first energy barrier. The second means for storingdata comprises a second means for storing a fixed magnetic moment havinga second fixed magnetic moment, and a second means for storing aprogrammable magnetic moment having a second programmable magneticmoment. The second means for storing data also comprises a second meansfor transferring spin polarization of electrons disposed between thesecond means for storing the fixed magnetic moment and the second meansfor storing the programmable magnetic moment. The second means forstoring data has a second energy barrier different from the first energybarrier.

Those of skill in the art will further appreciate that the variousillustrative logical blocks, modules, circuits, and algorithms describedin connection with the aspects disclosed herein may be implemented aselectronic hardware, instructions stored in memory or in anothercomputer readable medium and executed by a processor or other processingdevice, or combinations of both. The arbiters, master devices, and slavedevices described herein may be employed in any circuit, hardwarecomponent, integrated circuit (IC), or IC chip, as examples. Memorydisclosed herein may be any type and size of memory and may beconfigured to store any type of information desired. To clearlyillustrate this interchangeability, various illustrative components,blocks, modules, circuits, and steps have been described above generallyin terms of their functionality. How such functionality is implementeddepends upon the particular application, design choices, and/or designconstraints imposed on the overall system. Skilled artisans mayimplement the described functionality in varying ways for eachparticular application, but such implementation decisions should not beinterpreted as causing a departure from the scope of the presentdisclosure.

The various illustrative logical blocks, modules, and circuits describedin connection with the aspects disclosed herein may be implemented orperformed with a processor, a Digital Signal Processor (DSP), anApplication Specific Integrated Circuit (ASIC), a Field ProgrammableGate Array (FPGA) or other programmable logic device, discrete gate ortransistor logic, discrete hardware components, or any combinationthereof designed to perform the functions described herein. A processormay be a microprocessor, but in the alternative, the processor may beany conventional processor, controller, microcontroller, or statemachine. A processor may also be implemented as a combination ofcomputing devices (e.g., a combination of a DSP and a microprocessor, aplurality of microprocessors, one or more microprocessors in conjunctionwith a DSP core, or any other such configuration).

The aspects disclosed herein may be embodied in hardware and ininstructions that are stored in hardware, and may reside, for example,in Random Access Memory (RAM), flash memory, Read Only Memory (ROM),Electrically Programmable ROM (EPROM), Electrically ErasableProgrammable ROM (EEPROM), registers, a hard disk, a removable disk, aCD-ROM, or any other form of computer readable medium known in the art.An exemplary storage medium is coupled to the processor such that theprocessor can read information from, and write information to, thestorage medium. In the alternative, the storage medium may be integralto the processor. The processor and the storage medium may reside in anASIC. The ASIC may reside in a remote station. In the alternative, theprocessor and the storage medium may reside as discrete components in aremote station, base station, or server.

It is also noted that the operational steps described in any of theexemplary aspects herein are described to provide examples anddiscussion. The operations described may be performed in numerousdifferent sequences other than the illustrated sequences. Furthermore,operations described in a single operational step may actually beperformed in a number of different steps. Additionally, one or moreoperational steps discussed in the exemplary aspects may be combined. Itis to be understood that the operational steps illustrated in theflowchart diagrams may be subject to numerous different modifications aswill be readily apparent to one of skill in the art. Those of skill inthe art will also understand that information and signals may berepresented using any of a variety of different technologies andtechniques. For example, data, instructions, commands, information,signals, bits, symbols, and chips that may be referenced throughout theabove description may be represented by voltages, currents,electromagnetic waves, magnetic fields or particles, optical fields orparticles, or any combination thereof.

The previous description of the disclosure is provided to enable anyperson skilled in the art to make or use the disclosure. Variousmodifications to the disclosure will be readily apparent to thoseskilled in the art, and the generic principles defined herein may beapplied to other variations without departing from the spirit or scopeof the disclosure. Thus, the disclosure is not intended to be limited tothe examples and designs described herein, but is to be accorded thewidest scope consistent with the principles and novel features disclosedherein.

1. A semiconductor die, comprising: a first magnetic tunnel junction(MTJ) stack, comprising: a first pinned layer having a first pinnedlayer magnetic moment; a first free layer having a first free layermagnetic moment; and a first tunnel barrier layer disposed between thefirst pinned layer and the first free layer, wherein the first MTJ stackhas a first energy barrier; and a second MTJ stack, comprising: a secondpinned layer having a second pinned layer magnetic moment; a second freelayer having a second free layer magnetic moment; and a second tunnelbarrier layer disposed between the second pinned layer and the secondfree layer, wherein the second MTJ stack has a second energy barrierdifferent from the first energy barrier.
 2. The semiconductor die ofclaim 1, wherein: the first energy barrier of the first MTJ stack is anamount of energy to substantially invert a direction of the first freelayer magnetic moment in the first free layer; and the second energybarrier of the second MTJ stack is an amount of energy to substantiallyinvert a direction of the second free layer magnetic moment in thesecond free layer.
 3. The semiconductor die of claim 2, wherein: thefirst pinned layer further comprises a first material; and the secondpinned layer further comprises a second material different from thefirst material of the first pinned layer such that the second energybarrier of the second MTJ stack is different from the first energybarrier of the first MTJ stack.
 4. The semiconductor die of claim 3,wherein: the first material of the first pinned layer comprises one ormore of Cobalt (Co), Platinum (Pt), and Nickel (Ni); and the secondmaterial of the second pinned layer comprises one of more of Co, Pt, andNi.
 5. The semiconductor die of claim 2, wherein: the first free layerfurther comprises a first material; and the second free layer furthercomprises a second material different from the first material of thefirst free layer such that the second energy barrier of the second MTJstack is different from the first energy barrier of the first MTJ stack.6. The semiconductor die of claim 5, wherein: the first material of thefirst free layer comprises one or more of Cobalt (Co), Iron (Fe), andBoron (B) such that the first free layer has a first effectiveanisotropy energy constant; and the second material of the second freelayer comprises one or more of Co, Fe, and B such that the second freelayer has a second effective anisotropy energy constant less than thefirst effective anisotropy energy constant.
 7. The semiconductor die ofclaim 2, wherein: the first tunnel barrier layer further comprises afirst material; and the second tunnel barrier layer further comprises asecond material different from the first material of the first tunnelbarrier layer such that the second energy barrier of the second MTJstack is different from the first energy barrier of the first MTJ stack.8. The semiconductor die of claim 2, wherein: the first pinned layerfurther comprises a first width; and the second pinned layer furthercomprises a second width different from the first width of the firstpinned layer such that the second energy barrier of the second MTJ stackis different from the first energy barrier of the first MTJ stack. 9.The semiconductor die of claim 2, wherein: the first free layer furthercomprises a first width; and the second free layer further comprises asecond width different from the first width of the first free layer suchthat the second energy barrier of the second MTJ stack is different fromthe first energy barrier of the first MTJ stack.
 10. The semiconductordie of claim 9, wherein: the first width of the first free layercomprises a width less than thirty-five (35) nanometers (nm), betweenthirty-five (35) nm and seventy (70) nm, or greater than seventy (70)nm; and the second width of the second free layer comprises a width lessthan thirty-five (35) nm, between thirty-five (35) nm and seventy (70)nm, or greater than seventy (70) nm.
 11. The semiconductor die of claim2, wherein: the first tunnel barrier layer further comprises a firstwidth; and the second tunnel barrier layer further comprises a secondwidth different from the first width of the first tunnel barrier layersuch that the second energy barrier of the second MTJ stack is differentfrom the first energy barrier of the first MTJ stack.
 12. Thesemiconductor die of claim 11, wherein: the first width of the firsttunnel barrier layer is associated with a first resistance area productof the first tunnel barrier layer such that the first resistance areaproduct comprises a resistance area product of less than five (5)ohm-micrometers squared (Ωμm²), between five (5) and eight (8) Ωμm², orbetween eight (8) and ten (10) Ωμm²; and the second width of the secondtunnel barrier layer is associated with a second resistance area productof the second tunnel barrier layer such that the second resistance areaproduct comprises a resistance area product of less than five (5) Ωμm²,between five (5) and eight (8) Ωμm², or between eight (8) and ten (10)Ωμm².
 13. The semiconductor die of claim 1, further comprising: a thirdMTJ stack, comprising: a third pinned layer having a third pinned layermagnetic moment; a third free layer having a third free layer magneticmoment; and a third tunnel barrier layer disposed between the thirdpinned layer and the third free layer, wherein the third MTJ stack has athird energy barrier different from the first energy barrier and thesecond energy barrier.
 14. The semiconductor die of claim 1, furthercomprising: a first magneto-resistive random access memory (MRAM) bitcell of a first MRAM array, comprising: a first MTJ comprising a firsttop electrode layer and a first bottom electrode layer, wherein thefirst MTJ stack is disposed between the first top electrode layer andthe first bottom electrode layer; and a first access transistorcomprising a first gate, a first source, and a first drain, the firstaccess transistor coupled to the first MTJ; and a second MRAM bit cellof a second MRAM array, comprising: a second MTJ comprising a second topelectrode layer and a second bottom electrode layer, wherein the secondMTJ stack is disposed between the second top electrode layer and thesecond bottom electrode layer; and a second access transistor comprisinga second gate, a second source, and a second drain, the second accesstransistor coupled to the second MTJ.
 15. The semiconductor die of claim14, wherein the first MTJ of the first MRAM bit cell of the first MRAMarray and the second MTJ of the second MRAM bit cell of the second MRAMarray are in a same layer of the semiconductor die.
 16. Thesemiconductor die of claim 14, wherein: the first energy barrier of thefirst MTJ stack is lower than the second energy barrier of the secondMTJ stack; the first MRAM bit cell of the first MRAM array is configuredas an MRAM bit cell in embedded static random access memory (eSRAM); andthe second MRAM bit cell of the second MRAM array is configured as anMRAM bit cell in embedded dynamic random access memory (eDRAM).
 17. Thesemiconductor die of claim 14, wherein: the first energy barrier of thefirst MTJ stack is lower than the second energy barrier of the secondMTJ stack; the first MRAM bit cell of the first MRAM array is configuredas an MRAM bit cell in embedded static random access memory (eSRAM); andthe second MRAM bit cell of the second MRAM array is configured as anMRAM bit cell in eFlash memory.
 18. The semiconductor die of claim 14,wherein: the first energy barrier of the first MTJ stack is lower thanthe second energy barrier of the second MTJ stack; the first MRAM bitcell of the first MRAM array is configured as an MRAM bit cell inembedded dynamic random access memory (eDRAM); and the second MRAM bitcell of the second MRAM array is configured as an MRAM bit cell ineFlash memory.
 19. The semiconductor die of claim 1 integrated into adevice selected from the group consisting of: a set top box; anentertainment unit; a navigation device; a communications device; afixed location data unit; a mobile location data unit; a globalpositioning system (GPS) device; a mobile phone; a cellular phone; asmart phone; a session initiation protocol (SIP) phone; a tablet; aphablet; a server; a computer; a portable computer; a mobile computingdevice; a wearable computing device; a desktop computer; a personaldigital assistant (PDA); a monitor; a computer monitor; a television; atuner; a radio; a satellite radio; a music player; a digital musicplayer; a portable music player; a digital video player; a video player;a digital video disc (DVD) player; a portable digital video player; anautomobile; a vehicle component; avionics systems; a drone; and amulticopter.
 20. A semiconductor die, comprising: a first means forstoring data, comprising: a first means for storing a fixed magneticmoment having a first fixed magnetic moment; a first means for storing aprogrammable magnetic moment having a first programmable magneticmoment; and a first means for transferring spin polarization ofelectrons disposed between the first means for storing the fixedmagnetic moment and the first means for storing the programmablemagnetic moment, wherein the first means for storing data has a firstenergy barrier; and a second means for storing data, comprising: asecond means for storing a fixed magnetic moment having a second fixedmagnetic moment; a second means for storing a programmable magneticmoment having a second programmable magnetic moment; and a second meansfor transferring spin polarization of electrons disposed between thesecond means for storing the fixed magnetic moment and the second meansfor storing the programmable magnetic moment, wherein the second meansfor storing data has a second energy barrier different from the firstenergy barrier.
 21. A method of varying energy barriers of magnetictunnel junctions (MTJs) in different magneto-resistive random accessmemory (MRAM) arrays in a semiconductor die, comprising: forming a firstblocking layer over a second via of a second MRAM array, wherein thesecond via is in an interconnect layer of the semiconductor die;depositing a first MTJ stack film over a first via of a first MRAM arrayand at least a portion of the first blocking layer, wherein the firstvia is in the interconnect layer of the semiconductor die; depositing afirst top electrode film over the first MTJ stack film; depositing afirst mask over a portion of the first top electrode film over the firstMTJ stack film over the first via; removing a portion of the first topelectrode film and a portion of the first MTJ stack film not under thefirst mask to form a first top electrode layer over a first MTJ stackover the first via of the first MRAM array; removing at least a portionof the first blocking layer over the second via of the second MRAMarray; depositing a second MTJ stack film over the second via of thesecond MRAM array; depositing a second top electrode film over thesecond MTJ stack film; depositing a second mask over a portion of thesecond top electrode film over the second MTJ stack film over the secondvia; and removing a portion of the second top electrode film and aportion of the second MTJ stack film not under the second mask to form asecond top electrode layer over a second MTJ stack over the second viaof the second MRAM array.
 22. The method of claim 21, furthercomprising: removing the first mask; and forming a second blocking layerover the first MTJ stack of the first MRAM array, wherein: depositingthe second MTJ stack film over the second via of the second MRAM arraycomprises depositing the second MTJ stack film over the second via ofthe second MRAM array and at least a portion of the second blockinglayer.
 23. The method of claim 22, wherein: depositing the first MTJstack film over the first via of the first MRAM array and at least theportion of the first blocking layer comprises depositing a first pinnedfilm, a first tunnel barrier film, and a first free film over the firstvia of the first MRAM array and at least the portion of the firstblocking layer; and depositing the second MTJ stack film over the secondvia of the second MRAM array and at least the portion of the secondblocking layer comprises depositing a second pinned film, a secondtunnel barrier film, and a second free film over the second via of thesecond MRAM array and at least the portion of the second blocking layer,wherein the interconnect layer further comprises a bottom electrode filmover the first via of the first MRAM array and the second via of thesecond MRAM array.
 24. The method of claim 22, wherein: depositing thefirst MTJ stack film over the first via of the first MRAM array and atleast the portion of the first blocking layer comprises depositing afirst bottom electrode film, a first pinned film, a first tunnel barrierfilm, and a first free film over the first via of the first MRAM arrayand at least the portion of the first blocking layer; and depositing thesecond MTJ stack film over the second via of the second MRAM array andat least the portion of the second blocking layer comprises depositing asecond bottom electrode film, a second pinned film, a second tunnelbarrier film, and a second free film over the second via of the secondMRAM array and at least the portion of the second blocking layer. 25.The method of claim 23, further comprising: removing a portion of thebottom electrode film not under the first MTJ stack and the second MTJstack to form a first bottom electrode layer under the first MTJ stackand a second bottom electrode layer under the second MTJ stack.
 26. Themethod of claim 25, further comprising: forming a spacer film adjacentto the first MTJ stack and the second MTJ stack; depositing a dielectriclayer adjacent to the spacer film and over the first MTJ stack and thesecond MTJ stack; removing a portion of the dielectric layer over thefirst MTJ stack and the second MTJ stack to expose a first top surfaceof the first top electrode layer and a second top surface of the secondtop electrode layer; forming a first top electrode via over the firsttop surface of the first top electrode layer; and forming a second topelectrode via over the second top surface of the second top electrodelayer.
 27. The method of claim 26, wherein forming the spacer filmadjacent to the first MTJ stack and the second MTJ stack comprisesforming the spacer film adjacent to the first MTJ stack and the secondMTJ stack to expose a top surface of the interconnect layer of thesemiconductor die.
 28. The method of claim 22, further comprising:forming the first blocking layer over a third via of a third MRAM array,wherein the third via is in the interconnect layer of the semiconductordie; removing at least a portion of the first blocking layer over thethird via of the third MRAM array; forming the second blocking layerover a third MTJ stack of the third MRAM array; removing at least aportion of the second blocking layer over the third via of the thirdMRAM array; depositing a third MTJ stack film over the third via of thethird MRAM array; depositing a third top electrode film over the thirdMTJ stack film; depositing a third mask over a portion of the third topelectrode film over the third MTJ stack film over the third via; andremoving a portion of the third top electrode film and a portion of thethird MTJ stack film not under the third mask to form a third topelectrode layer over the third MTJ stack over the third via of the thirdMRAM array.
 29. A central processing unit (CPU) system, comprising: asystem bus; at least one CPU core communicatively coupled to the systembus; a memory controller communicatively coupled to the system bus; anda memory system communicatively coupled to the system bus, comprising: afirst magneto-resistive random access memory (MRAM) bit cell of a firstMRAM array, comprising: a first magnetic tunnel junction (MTJ) stack,comprising: a first pinned layer having a first pinned layer magneticmoment; a first free layer having a first free layer magnetic moment;and a first tunnel barrier layer disposed between the first pinned layerand the first free layer, wherein the first MTJ stack has a first energybarrier; a first MTJ comprising a first top electrode layer and a firstbottom electrode layer, wherein the first MTJ stack is disposed betweenthe first top electrode layer and the first bottom electrode layer; anda first access transistor comprising a first gate, a first source, and afirst drain, the first access transistor coupled to the first MTJ; and asecond MRAM bit cell of a second MRAM array, comprising: a second MTJstack, comprising: a second pinned layer having a second pinned layermagnetic moment; a second free layer having a second free layer magneticmoment; and a second tunnel barrier layer disposed between the secondpinned layer and the second free layer, wherein the second MTJ stack hasa second energy barrier different from the first energy barrier; asecond MTJ comprising a second top electrode layer and a second bottomelectrode layer, wherein the second MTJ stack is disposed between thesecond top electrode layer and the second bottom electrode layer; and asecond access transistor comprising a second gate, a second source, anda second drain, the second access transistor coupled to the second MTJ.